BS EN 62386-101:2014:2015 Edition
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Digital addressable lighting interface – General requirements. System components
| Published By | Publication Date | Number of Pages |
| BSI | 2015 | 84 |
IEC 62386-101:2014 is applicable to system components in a bus system for control by digital signals of electronic lighting equipment. This electronic lighting equipment should be in line with the requirements of IEC 61347, with the addition of d.c. supplies. This second edition cancels and replaces the first edition published in 2009. This edition constitutes a technical revision. This edition includes the following significant technical changes with respect to the previous edition: a) collection of all bus timing requirements defined in IEC 62386-101:2009 and IEC 62386-102:2009 and rework of the timing requirements to facilitate the preparation of a future control devices standard, taking particular account of the requirements for multi-master systems. The 10 % tolerances have been replaced by minimum and maximum timing values; b) integration of multi-master timing requirements; c) extension of the defined forward frames; d) addition of wiring requirements; e) improvement of the bus power supply requirements; f) improvement of test sequences and description of the test sequences in the form of pseudo code instead of flow charts. This publication is to be read in conjunction with /2.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 6 | English CONTENTS |
| 11 | INTRODUCTION Figures Figure 1 – IEC 62386 graphical overview |
| 12 | 1 Scope 2 Normative references 3 Terms and definitions |
| 17 | 4 General 4.1 Purpose 4.2 Version number 4.3 System structure and architecture Tables Table 1 – System components |
| 18 | 4.4 System information flow 4.5 Command types Figure 2 – System structure example Figure 3 – Communication between bus units (example) |
| 19 | 4.6 Bus units 4.6.1 Transmitters and receivers in bus units 4.6.2 Control gear 4.6.3 Input device 4.6.4 Single master application controller Table 2 – Transmitters and receivers in bus units |
| 20 | 4.6.5 Multi-master application controller 4.6.6 Sharing an interface Figure 4 – Example of a shared interface |
| 21 | 4.7 Bus power supply and load calculations 4.7.1 Current demand coverage 4.7.2 Maximum signal current compliance 4.7.3 Simplified system calculation 4.8 Wiring 4.8.1 Wiring structure 4.8.2 Wiring specification |
| 22 | 4.9 Insulation 4.10 Earthing of the bus 4.11 Power interruptions at bus units 4.11.1 Different levels of power interruptions 4.11.2 Short power interruptions of external power supply Table 3 – Power-interruption timing of external power Table 4 – Power-interruption timing of bus power |
| 23 | 4.11.3 External power cycle 4.11.4 Short interruptions of bus power supply 4.11.5 Bus power down 4.11.6 System start-up timing Table 5 – Short power interruptions |
| 24 | Figure 5 – Start up timing example Table 6 – Start-up timing |
| 25 | 5 Electrical specification 5.1 General 5.2 Marking of the interface 5.3 Capacitors between the interface and earth 5.4 Signal voltage rating Table 7 – System voltage levels Table 8 – Receiver voltage levels |
| 26 | 5.5 Signal current rating 5.6 Marking of bus powered bus unit 5.7 Signal rise time and fall time Table 9 – Transmitter voltage levels Table 10 – Current rating |
| 27 | Figure 6 – Maximum signal rise and fall time measurements Figure 7 – Minimum signal rise and fall time measurements Table 11 – Signal rise and fall times |
| 28 | 6 Bus power supply 6.1 General 6.2 Marking of the bus power supply terminals 6.3 Capacitors between the interface and earth 6.4 Voltage rating 6.5 Current rating 6.5.1 General current rating Table 12 – Bus power supply output voltage |
| 29 | 6.5.2 Single bus power supply current rating 6.5.3 Integrated bus power supply current rating 6.5.4 Dynamic behaviour of the bus power supply Table 13 – Bus power supply current rating Table 14 – Bus power supply dynamic behaviour |
| 30 | 6.6 Bus power supply timing requirements 6.6.1 Short power supply interruptions Figure 8 – Bus power supply current behaviour Figure 9 – Bus power supply voltage behaviour |
| 31 | 6.6.2 Short circuit behaviour 7 Transmission protocol structure 7.1 General 7.2 Bit encoding 7.2.1 Start bit and data bit encoding Figure 10 – Frame example Table 15 – Short circuit timing behaviour |
| 32 | 7.2.2 Stop condition encoding 7.3 Frame description 7.4 Frame types 7.4.1 16 bit forward frame 7.4.2 24 bit forward frame 7.4.3 Reserved forward frame 7.4.4 Backward frame 7.4.5 Proprietary forward frames Figure 11 – Bi-phase encoded bits |
| 33 | 8 Timing 8.1 Transmitter timing 8.1.1 Transmitter bit timing Figure 12 – Bit timing example |
| 34 | 8.1.2 Transmitter frame sequence timing 8.2 Receiver timing 8.2.1 Receiver bit timing Figure 13 – Settling time illustration Table 16 – Transmitter bit timing Table 17 – Transmitter settling time values |
| 35 | Table 18 – Receiver timing starting at the beginning of a logical bit Table 19 – Receiver timing starting at an edge inside of a logical bit |
| 36 | 8.2.2 Receiver bit timing violation 8.2.3 Receiver frame size violation 8.2.4 Receiver frame sequence timing Figure 14 – Receiver timing decision example |
| 37 | 8.2.5 Reception of backward frames 8.3 Multi-master transmitter timing 8.3.1 Multi-master transmitter bit timing Table 20 – Receiver settling time values Table 21 – Multi-master transmitter bit timing |
| 38 | 8.3.2 Multi-master transmitter frame sequence timing 9 Method of operation 9.1 Collision avoidance, collision detection and collision recovery 9.1.1 General Table 22 – Multi-master transmitter settling time values |
| 39 | 9.1.2 Collision avoidance 9.1.3 Collision detection Table 23 – Checking a logical bit, starting at an edge at the beginning of the bit |
| 40 | 9.1.4 Collision recovery Figure 15 – Collision detection timing decision example Table 24 – Checking a logical bit, starting at an edge inside the bit |
| 41 | 9.2 Transactions Figure 16 – Collision recovery example Table 25 – Collision recovery timing |
| 42 | 9.3 Send-twice forward frames and send-twice commands 9.4 Command iteration |
| 43 | 9.5 Usage of a shared interface 9.5.1 General 9.5.2 Backward frames 9.5.3 Forward frames 9.6 Use of multiple bus power supplies Table 26 – Transmitter command iteration timing Table 27 – Receiver command iteration timing |
| 44 | 9.7 Command execution 10 Declaration of variables 11 Definition of commands 12 Test procedures 12.1 General notes on test 12.1.1 Abbreviations 12.1.2 Ambient temperature |
| 45 | 12.1.3 External power supply voltage and frequency 12.1.4 Measurement requirements 12.1.5 Test signal generators and bus voltage sources 12.1.6 Deviation from documentation 12.1.7 Test setup 12.1.8 Notation |
| 46 | Table 28 – Function call keywords |
| 49 | Table 29 – Defined operators |
| 51 | 12.2 General interface tests 12.2.1 Label and literature check 12.2.2 Interface marking check |
| 52 | 12.2.3 Bus powered bus unit marking check |
| 54 | 12.2.4 Bus power supply marking check |
| 56 | 12.2.5 Insulation test |
| 57 | 12.2.6 Capacitor check 12.3 Bus power supply tests 12.3.1 Voltage rating test |
| 58 | 12.3.2 Voltage rise time test 12.3.3 Current rating test |
| 59 | Figure 17 – Current rating test signal |
| 60 | 12.3.4 Dynamic behaviour test Figure 18 – Dynamic behaviour test setup |
| 61 | Figure 19 – Dynamic behaviour test signal |
| 62 | 12.3.5 Power-on open circuit test |
| 63 | 12.3.6 Power-on timing test |
| 64 | 12.3.7 Power supply short interruptions test |
| 65 | 12.3.8 Power supply short circuit test |
| 66 | 12.3.9 Power supply current consumption test |
| 67 | 12.4 Control device tests 12.5 Control gear tests |
| 68 | Annex A (informative) Background information for systems A.1 Wiring information |
| 69 | A.2 System architectures A.2.1 General A.2.2 Single master architecture Table A.1 – Maximum cable length |
| 70 | A.2.3 Multi-master architecture with one application controller Figure A.1 – Single master architecture example |
| 71 | A.2.4 Multi-master architecture with more than one application controller Figure A.2 – Multi-master architecture example with one application controller |
| 72 | A.2.5 Multi-master architecture with integrated input device Figure A.3 – Multi-master architecture example with two application controllers |
| 73 | A.2.6 Multi-master architecture with integrated input device and power supply Figure A.4 – Multi-master architecture example with integrated input device |
| 74 | A.3 Collision detection Figure A.5 – Multi-master architecture example with integrate input device and bus power supply |
| 75 | A.4 Timing definition explanations A.4.1 General A.4.2 Receiver timing A.4.3 Transmitter timing Figure A.6 – Collision detection timing diagram |
| 76 | A.4.4 Grey areas A.5 Maximum current consumption calculation explanation A.5.1 Single bus power supply Figure A.7 – Transmitter and receiver timing illustration |
| 77 | A.5.2 Multiple bus power supplies Figure A.8 – Bus power supply current values Figure A.9 – Current demand coverage |
| 78 | A.5.3 Redundant bus power supplies Figure A.10 – Combination of 4 bus power supplies Figure A.11 – Redundant bus power supplies |
| 79 | A.6 Communication layer overview A.6.1 General A.6.2 Physical layer A.6.3 Data link layer A.6.4 Network layer Table A.2 – OSI layer model of IEC 62386 |
| 80 | A.6.5 Transport layer A.6.6 Session layer A.6.7 Presentation layer A.6.8 Application layer |
| 81 | Bibliography |
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