BS EN 62433-2:2010
$189.07
EMC IC modelling – Models of integrated circuits for EMI behavioural simulation. Conducted emissions modelling (ICEM-CE)
| Published By | Publication Date | Number of Pages |
| BSI | 2010 | 48 |
This part of IEC 62433 specifies macro-models for ICs to simulate conducted electromagnetic emissions on a printed circuit board. The model is commonly called Integrated Circuit Emission Model – Conducted Emission (ICEM-CE).
The ICEM-CE model can also be used for modelling an IC-die, a functional block and an Intellectual Property block (IP).
The ICEM-CE model can be used to model both digital and analogue ICs.
Basically, conducted emissions have two origins:
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conducted emissions through power supply terminals and ground reference structures;
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conducted emissions through input/output (I/O) terminals.
The ICEM-CE model addresses those two types of origins in a single approach.
This standard defines structures and components of the macro-model for EMI simulation taking into account the IC’s internal activities.
This standard gives general data, which can be implemented in different formats or languages such as IBIS, IMIC, SPICE, VHDL-AMS and Verilog. SPICE is however chosen as default simulation environment to cover all the conducted emissions.
This standard also specifies requirements for information that shall be incorporated in each ICEM-CE model or component part of the model for model circulation, but description syntax is not within the scope of this standard.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 6 | CONTENTS |
| 9 | 1 Scope 2 Normative references 3 Terms and definitions |
| 10 | 4 Philosophy 4.1 General 4.2 Conducted emission from core activity (digital culprit) Figures Figure 1 – Decomposition example of a digital IC for conducted emissions analysis |
| 11 | 4.3 Conducted emission from I/O activity 5 Basic components 5.1 General 5.2 Internal Activity (IA) Figure 2 – IA component |
| 12 | 5.3 Passive Distribution Network (PDN) Figure 3 – Example of IA characteristics in the time domain Figure 4 – Example of IA characteristics in the frequency domain |
| 13 | Figure 5 – Example of a four-terminal PDN using lumped elements Figure 6 – Example of a seven-terminal PDN using distributed elements |
| 14 | 6 IC macro-models 6.1 General 6.2 General IC macro-model Figure 7 – Example of a twelve-terminal PDN using matrix representation |
| 15 | 6.3 Block-based IC macro-model Figure 8 – General IC macro-model Figure 9 – Example of block component |
| 16 | Figure 10 – Example of block components for I/Os |
| 17 | Figure 11 – Example of IBC with two internal terminals Figure 12 – Relationship between blocks and IBC |
| 18 | Figure 13 – Block-based IC macro-model |
| 19 | 6.4 Sub-model-based IC macro-model Figure 14 – Example of block-based IC macro-model |
| 20 | Figure 15 – Example of simple sub-model Figure 16 – Sub-model-based IC macro-model |
| 21 | 7 Requirements for parameter extraction 7.1 General 7.2 Environmental extraction constraints 7.3 IA parameter extraction 7.4 PDN parameter extraction 7.5 IBC parameter extraction |
| 22 | Annex A (informative) Model parameter generation Table A.1 – Typical parameters for CMOS logic technologies |
| 23 | Table A.2 – Typical number of logic gates vs. CPU technology Table A.3 – R, L and C parameters for various package types |
| 24 | Figure A.1 – Typical characterization current gate schematic Figure A.2 – Current peak during switching transition |
| 25 | Figure A.3 – Example of IA extraction procedure from design Figure A.4 – Technology Influence |
| 26 | Figure A.5 – Final current waveform for a program period Figure A.6 – Comparison between measurement and simulation |
| 27 | Figure A.7 – Lumped element model of a package |
| 28 | Figure A.8 – Circuit structure of the netlist |
| 29 | Figure A.9 – Principle of the IA computation Figure A.10 – Process involved to model iA(t) |
| 30 | Figure A.11 – iExt(t) measured using IEC 61967-4 Figure A.12 – iA(t)and iExt(t) profiles |
| 32 | Figure A.13 – Example of a hardware set-up used to extract the PDN parameters Figure A.14 – Miniature 50 Ω coaxial connectors |
| 33 | Figure A.15 – Impedance probe using two miniature coaxial connectors Figure A.16 – Open and short terminations Figure A.17 – Measurement probe model |
| 34 | Figure A.18 – De-embedding principle |
| 35 | Figure A.19 – Example of a predefined PDN structure Table A.4 – Measurement configurations and extracted RLC parameters |
| 36 | Figure A.20 – RL configuration Figure A.21 – RLC configuration |
| 37 | Figure A.22 – RLC with magnetic coupling configuration Figure A.23 – Impedance seen from Vcc and Gnd |
| 38 | Figure A.24 – Complete PDN component |
| 39 | Figure A.25 – Set-up for correlation (left), measurement and prediction (right) Figure A.26 – Set-up used to measure the internal decoupling capacitor |
| 40 | Annex B (informative) Decoupling capacitors optimization Figure B.1 – Equivalent schematic of the complete electronic system |
| 41 | Figure B.2 – Impedance prediction and measurements |
| 42 | Annex C (informative) Conducted emission prediction Figure C.1 – IEC 61967-4 test set-up standard Figure C.2 – Comparison between prediction and measurement |
| 43 | Annex D (informative) Conducted emission prediction at PCB level Figure D.1 – Prediction of Vddc noise level at PCB level |
| 44 | Figure D.2 – Good agreements on the noise envelope |
| 45 | Bibliography |
