BS EN 62433-2:2017
$215.11
EMC IC modelling – Models of integrated circuits for EMI behavioural simulation. Conducted emissions modelling (ICEM-CE)
| Published By | Publication Date | Number of Pages |
| BSI | 2017 | 112 |
IEC 62433-2:2017 specifies macro-models for an Integrated Circuit (IC) to simulate conducted electromagnetic emissions on a printed circuit board. The model is commonly called Integrated Circuit Emission Model – Conducted Emission (ICEM-CE). The ICEM-CE macro-model can also be used for modelling an IC-die, a functional block and an Intellectual Property (IP) block. The ICEM-CE macro-model can be used to model both digital and analogue ICs. This edition includes the following significant technical changes with respect to the previous edition: Incorporation of an XML based exchange format for model representation.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 2 | National foreword |
| 5 | Annex ZA(normative)Normative references to international publicationswith their corresponding European publications |
| 7 | English CONTENTS |
| 12 | FOREWORD |
| 14 | 1 Scope 2 Normative references 3 Terms, definitions, abbreviations and conventions 3.1 Terms and definitions |
| 16 | 3.2 Abbreviations 3.3 Conventions 4 Philosophy 4.1 General |
| 17 | 4.2 Conducted emission from core activity (digital culprit) 4.3 Conducted emission from I/O activity 4.4 Data exchange format Figures Figure 1 – Decomposition example of a digital IC for conducted emissions analysis |
| 18 | 5 ICEM-CE basic components 5.1 General 5.2 Internal Activity (IA) 5.2.1 General Figure 2 – IA component in the case of a current source |
| 19 | 5.2.2 Examples of IA 5.3 Passive Distribution Network (PDN) 5.3.1 General Figure 3 – Example of IA characteristics in the time domain Figure 4 – Example of IA characteristics in the frequency domain |
| 20 | 5.3.2 Examples of PDN Figure 5 – Example of a four-terminal PDN using lumped elements |
| 21 | 6 IC macro-models 6.1 Types of IC macro-models 6.2 General IC macro-model Figure 6 – Example of a seven-terminal PDN using distributed elements Figure 7 – Example of a twelve-terminal PDN using matrix representation |
| 22 | 6.3 Block-based IC macro-model 6.3.1 Block component Figure 8 – General IC macro-model |
| 23 | 6.3.2 Inter-Block Coupling component (IBC) Figure 9 – Example of block component with a single IA Figure 10 – Example of block components for I/Os |
| 24 | 6.3.3 Block-based IC macro-model structure Figure 11 – Example of IBC with four internal terminals Figure 12 – Relationship between blocks and IBC |
| 25 | Figure 13 – Block-based IC macro-model |
| 26 | 6.4 Sub-model-based IC macro-model 6.4.1 Sub-model component Figure 14 – Example of block-based IC macro-model Figure 15 – Example of simple sub-model |
| 27 | 6.4.2 Sub-model-based IC macro-model structure Figure 16 – Sub-model-based IC macro-model |
| 28 | 7 CEML format 7.1 General Figure 17 – CEML inheritance hierarchy |
| 29 | 7.2 CEML structure 7.3 Global keywords 7.4 Header section |
| 30 | 7.5 Lead definitions Tables Table 1 – Attributes of Lead keyword in the Lead_definitions section |
| 31 | 7.6 SPICE macro-models Table 2 – Compatibility between the Mode and Type fields for correct CEML annotation Table 3 – Subckt definition |
| 33 | 7.7 Validity section 7.7.1 General Figure 18 – Example of a netlist file defining a sub-circuit Table 4 – Definition of the Validity section |
| 34 | 7.7.2 Attribute definitions |
| 36 | 7.8 PDN 7.8.1 General |
| 37 | 7.8.2 Attribute definitions Table 5 – Definition of the Lead keyword for Pdn section |
| 40 | Table 6 – Valid data formats and their default units in the Pdn section Table 7 – Valid file extensions in the Pdn section |
| 41 | 7.8.3 Description Table 8 – Valid fields of the Lead keyword in the Pdn section |
| 43 | Figure 19 – PDN represented as S-parameters in Touchstone format |
| 44 | Table 9 – Netlist definition |
| 45 | 7.9 IBC 7.9.1 General 7.9.2 Attribute definitions |
| 46 | Table 10 – Differences between the Pdn and Ibc section fields Table 11 – Valid fields of the Lead keyword for IBC definition |
| 47 | 7.10 IA 7.10.1 General 7.10.2 Attribute definitions Table 12 – Definition of the Lead keyword in the Ia section |
| 48 | Table 13 – Voltage and Current definition Table 14 – Valid file extensions in the Ia section |
| 49 | Table 15 – Definition of the Pulse keyword in the Voltage or Current section Table 16 – Base units of the Pulse section’s fields |
| 50 | Figure 20 – Simulated IA waveform with corresponding parameters |
| 51 | 7.10.3 Description Table 17 – Valid data formats and their default units for the Voltage and Current elements |
| 52 | 8 Requirements for parameter extraction 8.1 General 8.2 Environmental extraction constraints 8.3 IA parameter extraction 8.4 PDN parameter extraction |
| 53 | 8.5 IBC parameter extraction |
| 54 | Annex A (normative)Preliminary definitions for XML representation A.1 XML basics A.1.1 XML declaration A.1.2 Basic elements A.1.3 Root element |
| 55 | A.1.4 Comments A.1.5 Line terminations A.1.6 Element hierarchy A.1.7 Element attributes A.2 Keyword requirements A.2.1 General |
| 56 | A.2.2 Keyword characters A.2.3 Keyword syntax A.2.4 File structure |
| 57 | Figure A.1 – Multiple XML (CEML) files Figure A.2 – XML files with data files (*.dat) |
| 58 | A.2.5 Values Figure A.3 – XML files with additional files |
| 59 | Table A.1 – Valid logarithmic units |
| 61 | Annex B (normative)CEML valid keywords and usage B.1 Root element keywords |
| 62 | B.2 File header keywords |
| 63 | B.3 Validity section keywords |
| 64 | B.4 Global keywords B.5 Lead Keyword |
| 65 | B.6 Lead_definitions section attributes B.7 Macromodels section attributes |
| 66 | B.8 Pdn section keywords B.8.1 Lead element keywords |
| 68 | B.8.2 Netlist section keywords B.9 Ibc section keywords B.9.1 Lead element keywords |
| 70 | B.9.2 Netlist section keywords B.10 Ia section keywords B.10.1 Lead element keywords |
| 71 | B.10.2 Voltage section keywords |
| 73 | B.10.3 Current section keywords |
| 75 | Annex C (informative)Example of ICEM-CE macro-model in CEML format C.1 General C.2 PDN and IBC sub-model Figure C.1 – Example pin-out of a microcontroller and the modelled pins |
| 76 | C.3 IA sub-model Figure C.2 – PDN sub-model topology |
| 77 | Figure C.3 – IA sub-model topology Figure C.4 – IA of digital block in frequency domain |
| 78 | C.4 Frequency domain ICEM-CE in CEML Figure C.5 – IA of digital block in time domain |
| 80 | C.5 Time domain ICEM-CE in CEML |
| 82 | Annex D (informative)Conversions between parameter types D.1 General D.2 Conversion for one-port PDN D.3 Conversion for two-port PDN Table D.1 – One-port conversion |
| 83 | Table D.2 – Two-port conversion |
| 84 | Annex E (informative)Model parameter generation E.1 General E.2 Default structure and values E.2.1 General E.2.2 IA parameters |
| 85 | E.2.3 PDN parameters Table E.1 – Typical parameters for CMOS logic technologies Table E.2 – Typical number of logic gates vs. CPU technology |
| 86 | E.3 Model parameter generation from design information E.3.1 General E.3.2 IA parameters Table E.3 – R, L and C parameters for various package types |
| 87 | Figure E.1 – Typical characterization current gate schematic Figure E.2 – Current peak during switching transition |
| 88 | Figure E.3 – Example of IA extraction procedure from design Figure E.4 – Technology Influence |
| 89 | Figure E.5 – Final current waveform for a program period Figure E.6 – Comparison between measurement and simulation |
| 90 | E.3.3 PDN parameters Figure E.7 – Example lumped element model of a package |
| 92 | E.4 Model parameter generation from measurements E.4.1 IA parameters Figure E.8 – Circuit structure of the netlist |
| 93 | Figure E.9 – Principle of the IA computation in the frequency domain |
| 94 | Figure E.10 – Process involved to model iA(t) Figure E.11 – iExt(t) measured using IEC 61967-4 |
| 95 | E.4.2 PDN parameters Figure E.12 – iA(t)and iExt(t) profiles Figure E.13 – Conventional one-port S-parameter measurement |
| 96 | Figure E.14 – Two-port method for low impedance measurement Figure E.15 – Two-port method for high impedance measurement |
| 97 | Figure E.16 – Example of a hardware set-up used to extract the PDN parameters |
| 98 | Figure E.17 – Miniature 50 Ω coaxial connectors Figure E.18 – Impedance probe using two miniature coaxial connectors Figure E.19 – Open and short terminations |
| 99 | Figure E.20 – Measurement probe model Figure E.21 – De-embedding principle |
| 100 | Figure E.22 – Example of a predefined PDN structure Table E.4 – Measurement configurations and extracted RLC parameters |
| 101 | Figure E.23 – RL configuration |
| 102 | Figure E.24 – RLC configuration Figure E.25 – RLC with magnetic coupling configuration Figure E.26 – Impedance seen from Vcc and Gnd |
| 103 | Figure E.27 – Complete PDN component |
| 104 | Figure E.28 – Set-up for correlation (left), measurement and prediction model (right) Figure E.29 – Set-up used to measure the internal decoupling capacitor |
| 105 | Annex F (informative)Decoupling capacitors optimization Figure F.1 – Equivalent schematic of the complete electronic system |
| 106 | Figure F.2 – Impedance prediction and measurements |
| 107 | Annex G (informative)Conducted emission prediction Figure G.1 – IEC 61967-4 test set-up standard Figure G.2 – Comparison between prediction and measurement |
| 108 | Annex H (informative)Conducted emission prediction at PCB level Figure H.1 – Prediction of ETVddc noise level at PCB level |
| 109 | Figure H.2 – Good agreements on the noise envelope |
| 110 | Bibliography |
