IEC 62680-2-1:2015 defines an industry-standard USB. The specification describes the bus attributes, the protocol definition, types of transactions, bus management, and the programming interface required to design and build systems and peripherals that are compliant with this standard. The goal is to enable such devices from different vendors to interoperate in an open architecture. The specification is intended as an enhancement to the PC architecture, spanning portable, business desktop, and home environments. It is intended that the specification allow system OEMs and peripheral developers adequate room for product versatility and market differentiation without the burden of carrying obsolete interfaces or losing compatibility.

PDF Catalog

PDF Pages	PDF Title
5	FOREWORD
7	INTRODUCTION
8	CONTENTS
32	1 Chapter 1 Introduction 1.1 Motivation 1.2 Objective of the Specification
33	1.3 Scope of the Document 1.4 USB Product Compliance 1.5 Document Organization
34	2 Chapter 2 Terms and Abbreviations
40	3 Chapter 3 Background 3.1 Goals for the Universal Serial Bus 3.2 Taxonomy of Application Space Figures Figure 3-1 – Application Space Taxonomy
41	3.3 Feature List
43	4 Chapter 4 Architectural Overview 4.1 USB System Description 4.1.1 Bus Topology
44	4.2 Physical Interface Figure 4-1 – Bus Topology
45	4.2.1 Electrical 4.2.2 Mechanical 4.3 Power Figure 4-2 – USB Cable
46	4.3.1 Power Distribution 4.3.2 Power Management 4.4 Bus Protocol 4.5 Robustness
47	4.5.1 Error Detection 4.5.2 Error Handling 4.6 System Configuration 4.6.1 Attachment of USB Devices 4.6.2 Removal of USB Devices
48	4.6.3 Bus Enumeration 4.7 Data Flow Types 4.7.1 Control Transfers 4.7.2 Bulk Transfers 4.7.3 Interrupt Transfers
49	4.7.4 Isochronous Transfers 4.7.5 Allocating USB Bandwidth 4.8 USB Devices 4.8.1 Device Characterizations
50	4.8.2 Device Descriptions Figure 4-3 – A Typical Hub
51	Figure 4-4 – Hubs in a Desktop Computer Environment
52	4.9 USB Host: Hardware and Software 4.10 Architectural Extensions
53	5 Chapter 5 USB Data Flow Model 5.1 Implementer Viewpoints Figure 5-1 – Simple USB Host/Device View
54	5.2 Bus Topology Figure 5-2 – USB Implementation Areas
55	5.2.1 USB Host 5.2.2 USB Devices Figure 5-3 – Host Composition
56	5.2.3 Physical Bus Topology Figure 5-4 – Physical Device Composition Figure 5-5 – USB Physical Bus Topology
57	5.2.4 Logical Bus Topology Figure 5-6 – Multiple Full-speed Buses in a High-speed System
58	5.2.5 Client Software-to-function Relationship 5.3 USB Communication Flow Figure 5-7 – USB Logical Bus Topology Figure 5-8 – Client Software-to-function Relationships
59	Figure 5-9 – USB Host/Device Detailed View
60	5.3.1 Device Endpoints Figure 5-10 – USB Communication Flow
61	5.3.2 Pipes
63	5.3.3 Frames and Microframes 5.4 Transfer Types
64	5.4.1 Table Calculation Examples
65	5.5 Control Transfers 5.5.1 Control Transfer Data Format
66	5.5.2 Control Transfer Direction 5.5.3 Control Transfer Packet Size Constraints
67	5.5.4 Control Transfer Bus Access Constraints
68	Tables Table 5-1 – Low-speed Control Transfer Limits
69	5.5.5 Control Transfer Data Sequences Table 5-2 – Full-speed Control Transfer Limits Table 5-3 – High-speed Control Transfer Limits
70	5.6 Isochronous Transfers 5.6.1 Isochronous Transfer Data Format 5.6.2 Isochronous Transfer Direction 5.6.3 Isochronous Transfer Packet Size Constraints
71	Table 5-4 – Full-speed Isochronous Transaction Limits
72	5.6.4 Isochronous Transfer Bus Access Constraints Table 5-5 – High-speed Isochronous Transaction Limits
73	5.6.5 Isochronous Transfer Data Sequences 5.7 Interrupt Transfers 5.7.1 Interrupt Transfer Data Format 5.7.2 Interrupt Transfer Direction 5.7.3 Interrupt Transfer Packet Size Constraints
74	5.7.4 Interrupt Transfer Bus Access Constraints
75	Table 5-6 – Low-speed Interrupt Transaction Limits Table 5-7 – Full-speed Interrupt Transaction Limits
76	Table 5-8 – High-speed Interrupt Transaction Limits
77	5.7.5 Interrupt Transfer Data Sequences 5.8 Bulk Transfers 5.8.1 Bulk Transfer Data Format 5.8.2 Bulk Transfer Direction 5.8.3 Bulk Transfer Packet Size Constraints
78	5.8.4 Bulk Transfer Bus Access Constraints
79	5.8.5 Bulk Transfer Data Sequences Table 5-9 – Full-speed Bulk Transaction Limits Table 5-10 – High-speed Bulk Transaction Limits
80	5.9 High-Speed, High Bandwidth Endpoints 5.9.1 High Bandwidth Interrupt Endpoints Table 5-11 – wMaxPacketSize Field of Endpoint Descriptor
81	5.9.2 High Bandwidth Isochronous Endpoints Figure 5-11 – Data Phase PID Sequence for Isochronous IN High Bandwidth Endpoints
82	5.10 Split Transactions 5.11 Bus Access for Transfers Figure 5-12 – Data Phase PID Sequence for Isochronous OUT High Bandwidth Endpoints
83	5.11.1 Transfer Management Figure 5-13 – USB Information Conversion From Client Software to Bus
85	5.11.2 Transaction Tracking
86	Figure 5-14 – Transfers for Communication Flows
87	5.11.3 Calculating Bus Transaction Times Figure 5-15 – Arrangement of IRPs to Transactions/(Micro)frames
89	5.11.4 Calculating Buffer Sizes in Functions and Software 5.11.5 Bus Bandwidth Reclamation 5.12 Special Considerations for Isochronous Transfers
91	5.12.1 Example Non-USB Isochronous Application Figure 5-16 – Non-USB Isochronous Example
92	5.12.2 USB Clock Model
93	Figure 5-17 – USB Full-speed Isochronous Application
94	5.12.3 Clock Synchronization 5.12.4 Isochronous Devices
95	Table 5-12 – Synchronization Characteristics
99	Figure 5-18 – Example Source/Sink Connectivity
101	Table 5-13 – Connection Requirements
102	5.12.5 Data Prebuffering
103	5.12.6 SOF Tracking 5.12.7 Error Handling Figure 5-19 – Data Prebuffering
104	5.12.8 Buffering for Rate Matching
105	Figure 5-20 – Packet and Buffer Size Formulas for Rate-matched Isochronous Transfers
106	6 Chapter 6 Mechanical 6.1 Architectural Overview 6.2 Keyed Connector Protocol Figure 6-1 – Keyed Connector Protocol
107	6.3 Cable 6.4 Cable Assembly 6.4.1 Standard Detachable Cable Assemblies
108	Figure 6-2 – USB Standard Detachable Cable Assembly
109	6.4.2 High-/full-speed Captive Cable Assemblies
110	Figure 6-3 – USB High-/full-speed Hardwired Cable Assembly
111	6.4.3 Low-speed Captive Cable Assemblies
112	Figure 6-4 – USB Low-speed Hardwired Cable Assembly
113	6.4.4 Prohibited Cable Assemblies 6.5 Connector Mechanical Configuration and Material Requirements
114	6.5.1 USB Icon Location 6.5.2 USB Connector Termination Data Figure 6-5 – USB Icon Figure 6-6 – Typical USB Plug Orientation
115	6.5.3 Series “A” and Series “B” Receptacles Table 6-1 – USB Connector Termination Assignment
116	Figure 6-7 – USB Series “A” Receptacle Interface and Mating Drawing
117	Figure 6-8 – USB Series “B” Receptacle Interface and Mating Drawing
118	6.5.4 Series “A” and Series “B” Plugs
119	Figure 6-9 – USB Series “A” Plug Interface Drawing
120	Figure 6-10 – USB Series “B” Plug Interface Drawing
121	6.6 Cable Mechanical Configuration and Material Requirements
122	6.6.1 Description 6.6.2 Construction Figure 6-11 – Typical High-/full-speed Cable Construction
123	Table 6-2 – Power Pair Table 6-3 – Signal Pair
124	Table 6-4 – Drain Wire Signal Pair
125	6.6.3 Electrical Characteristics 6.6.4 Cable Environmental Characteristics 6.6.5 Listing Table 6-5 – Nominal Cable Diameter Table 6-6 – Conductor Resistance
126	6.7 Electrical, Mechanical, and Environmental Compliance Standards Table 6-7 – USB Electrical, Mechanical, and Environmental Compliance Standards
131	6.7.1 Applicable Documents 6.8 USB Grounding 6.9 PCB Reference Drawings
132	Figure 6-12 – Single Pin-type Series “A” Receptacle
133	Figure 6-13 – Dual Pin-type Series “A” Receptacle
134	Figure 6-14 – Single Pin-type Series “B” Receptacle
135	7 Chapter 7 Electrical 7.1 Signaling Figure 7-1 – Example High-speed Capable Transceiver Circuit
137	Table 7-1 – Description of Functional Elements in the Example Shown in Figure 7-1
138	7.1.1 USB Driver Characteristics Figure 7-2 – Maximum Input Waveforms for USB Signaling
139	Figure 7-3 – Example Full-speed CMOS Driver Circuit (non High-speed capable)
141	Figure 7-4 – Full-speed Buffer V/I Characteristics
142	Figure 7-5 – Full-speed Buffer V/I Characteristics for High-speed Capable Transceiver
143	Figure 7-6 – Full-speed Signal Waveforms Figure 7-7 – Low-speed Driver Signal Waveforms
145	7.1.2 Data Signal Rise and Fall, Eye Patterns Figure 7-8 – Data Signal Rise and Fall Time
146	Figure 7-9 – Full-speed Load Figure 7-10 – Low-speed Port Loads Figure 7-11 – Measurement Planes
147	Figure 7-12 – Transmitter/Receiver Test Fixture
148	Figure 7-13 – Template 1
149	Figure 7-14 – Template 2
150	Figure 7-15 – Template 3
151	Figure 7-16 – Template 4
152	Figure 7-17 – Template 5
153	Figure 7-18 – Template 6
154	7.1.3 Cable Skew 7.1.4 Receiver Characteristics
155	Figure 7-19 – Differential Input Sensitivity Range for Low-/full-speed
156	7.1.5 Device Speed Identification Figure 7-20 – Full-speed Device Cable and Resistor Connections
157	7.1.6 Input Characteristics Figure 7-21 – Low-speed Device Cable and Resistor Connections
158	Figure 7-22 – Placement of Optional Edge Rate Control Capacitors for Low-/full-speed Figure 7-23 – Diagram for High-speed Loading Equivalent Circuit
160	7.1.7 Signaling Levels Table 7-2 – Low-/full-speed Signaling Levels
162	Figure 7-24 – Upstream Facing Full-speed Port Transceiver Figure 7-25 – Downstream Facing Low-/full-speed Port Transceiver
163	Table 7-3 – High-speed Signaling Levels
164	Table 7-3 – High-speed Signaling Levels (Continued)
165	Figure 7-26 – Low-/full-speed Disconnect Detection Figure 7-27 – Full-/high-speed Device Connect Detection Figure 7-28 – Low-speed Device Connect Detection
166	Figure 7-29 – Power-on and Connection Events Timing
168	Figure 7-30 – Low-/full-speed Packet Voltage Levels
173	7.1.8 Data Encoding/Decoding 7.1.9 Bit Stuffing Figure 7-31 – NRZI Data Encoding
174	Figure 7-32 – Bit Stuffing Figure 7-33 – Illustration of Extra Bit Preceding EOP (Full-/low-speed)
175	7.1.10 Sync Pattern Figure 7-34 – Flow Diagram for Bit Stuffing Figure 7-35 – Sync Pattern (Low-/full-speed)
176	7.1.11 Data Signaling Rate 7.1.12 Frame Interval
177	7.1.13 Data Source Signaling Figure 7-36 – Data Jitter Taxonomy
178	7.1.14 Hub Signaling Timings Figure 7-37 – SE0 for EOP Width Timing
179	Figure 7-38 – Hub Propagation Delay of Full-speed Differential Signals
180	7.1.15 Receiver Data Jitter
181	Table 7-4 – Full-speed Jitter Budget
182	7.1.16 Cable Delay Table 7-5 – Low-speed Jitter Budget
183	7.1.17 Cable Attenuation Figure 7-39 – Full-speed Cable Delay Figure 7-40 – Low-speed Cable Delay
184	7.1.18 Bus Turn-around Time and Inter-packet Delay Table 7-6 – Maximum Allowable Cable Loss
185	7.1.19 Maximum End-to-end Signal Delay
186	7.1.20 Test Mode Support Figure 7-41 – Worst-case End-to-end Signal Delay Model for Low-/full-speed
187	7.2 Power Distribution 7.2.1 Classes of Devices
189	Figure 7-42 – Compound Bus-powered Hub
190	Figure 7-43 – Compound Self-powered Hub
191	Figure 7-44 – Low-power Bus-powered Function Figure 7-45 – High-power Bus-powered Function
192	7.2.2 Voltage Drop Budget 7.2.3 Power Control During Suspend/Resume Figure 7-46 – Self-powered Function Figure 7-47 – Worst-case Voltage Drop Topology (Steady State)
193	7.2.4 Dynamic Attach and Detach Figure 7-48 – Typical Suspend Current Averaging Profile
194	7.3 Physical Layer 7.3.1 Regulatory Requirements
195	7.3.2 Bus Timing/Electrical Characteristics Table 7-7 – DC Electrical Characteristics
196	Table 7-7 – DC Electrical Characteristics (Continued)
197	Table 7-7 – DC Electrical Characteristics (Continued) Table 7-8 – High-speed Source Electrical Characteristics
198	Table 7-9 – Full-speed Source Electrical Characteristics
199	Table 7-10 – Low-speed Source Electrical Characteristics
200	Table 7-11 – Hub/Repeater Electrical Characteristics
201	Table 7-12 – Cable Characteristics (Note 14)
202	Table 7-13 – Hub Event Timings
203	Table 7-13 – Hub Event Timings (Continued) Table 7-14 – Device Event Timings
204	Table 7-14 – Device Event Timings (Continued)
205	7.3.3 Timing Waveforms Figure 7-49 – Differential Data Jitter for Low-/full-speed Figure 7-50 – Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed Figure 7-51 – Receiver Jitter Tolerance for Low-/full-speed
206	Figure 7-52 – Hub Differential Delay, Differential Jitter, and SOP Distortion for Low-/full-speed
207	Figure 7-53 – Hub EOP Delay and EOP Skew for Low-/full-speed
208	8 Chapter 8 Protocol Layer 8.1 Byte/Bit Ordering 8.2 SYNC Field 8.3 Packet Field Formats 8.3.1 Packet Identifier Field Figure 8-1 – PID Format
209	8.3.2 Address Fields Table 8-1 – PID Types
210	8.3.3 Frame Number Field 8.3.4 Data Field Figure 8-2 – ADDR Field Figure 8-3 – Endpoint Field
211	8.3.5 Cyclic Redundancy Checks Figure 8-4 – Data Field Format
212	8.4 Packet Formats 8.4.1 Token Packets 8.4.2 Split Transaction Special Token Packets Figure 8-5 – Token Format
213	Figure 8-6 – Packets in a Start-split Transaction Figure 8-7 – Packets in a Complete-split Transaction
214	Figure 8-8 – Relationship of Interrupt IN Transaction to High-speed Split Transaction Figure 8-9 – Relationship of Interrupt OUT Transaction to High-speed Split OUT Transaction
215	Figure 8-10 – Start-split (SSPLIT) Token Figure 8-11 – Port Field
216	Table 8-2 – Isochronous OUT Payload Continuation Encoding
217	8.4.3 Start-of-Frame Packets Figure 8-12 – Complete-split (CSPLIT) Transaction Token Figure 8-13 – SOF Packet Table 8-3 – Endpoint Type Values in Split Special Token
218	8.4.4 Data Packets Figure 8-14 – Relationship between Frames and Microframes
219	8.4.5 Handshake Packets Figure 8-15 – Data Packet Format Figure 8-16 – Handshake Packet
220	8.4.6 Handshake Responses Table 8-4 – Function Responses to IN Transactions
221	8.5 Transaction Packet Sequences Table 8-5 – Host Responses to IN Transactions Table 8-6 – Function Responses to OUT Transactions in Order of Precedence
222	Figure 8-17 – Legend for State Machines
223	Figure 8-18 – State Machine Context Overview Figure 8-19 – Host Controller Top Level Transaction State Machine Hierarchy Overview
224	Figure 8-20 – Host Controller Non-split Transaction State Machine Hierarchy Overview Figure 8-21 – Device Transaction State Machine Hierarchy Overview
225	Figure 8-22 – Device Top Level State Machine
226	Figure 8-23 – Device_process_Trans State Machine
227	Figure 8-24 – Dev_do_OUT State Machine
228	Figure 8-25 – Dev_do_IN State Machine
229	Figure 8-26 – HC_Do_nonsplit State Machine
230	8.5.1 NAK Limiting via Ping Flow Control
231	Figure 8-27 – Host High-speed Bulk OUT/Control Ping State Machine
232	Figure 8-28 – Dev_HS_ping State Machine
233	Figure 8-29 – Device High-speed Bulk OUT /Control State Machine
234	8.5.2 Bulk Transactions Figure 8-30 – Bulk Transaction Format
235	Figure 8-31 – Bulk/Control/Interrupt OUT Transaction Host State Machine
236	Figure 8-32 – Bulk/Control/Interrupt OUT Transaction Device State Machine
237	Figure 8-33 – Bulk/Control/Interrupt IN Transaction Host State Machine
238	Figure 8-34 – Bulk/Control/Interrupt IN Transaction Device State Machine Figure 8-35 – Bulk Reads and Writes
239	8.5.3 Control Transfers Figure 8-36 – Control SETUP Transaction
240	Figure 8-37 – Control Read and Write Sequences Table 8-7 – Status Stage Responses
242	8.5.4 Interrupt Transactions 8.5.5 Isochronous Transactions Figure 8-38 – Interrupt Transaction Format
243	Figure 8-39 – Isochronous Transaction Format
244	Figure 8-40 – Isochronous OUT Transaction Host State Machine Figure 8-41 – Isochronous OUT Transaction Device State Machine
245	Figure 8-42 – Isochronous IN Transaction Host State Machine
246	8.6 Data Toggle Synchronization and Retry Figure 8-43 – Isochronous IN Transaction Device State Machine
247	8.6.1 Initialization via SETUP Token 8.6.2 Successful Data Transactions Figure 8-44 – SETUP Initialization Figure 8-45 – Consecutive Transactions
248	8.6.3 Data Corrupted or Not Accepted 8.6.4 Corrupted ACK Handshake Figure 8-46 – NAKed Transaction with Retry Figure 8-47 – Corrupted ACK Handshake with Retry
249	8.6.5 Low-speed Transactions Figure 8-48 – Low-speed Transaction
250	8.7 Error Detection and Recovery 8.7.1 Packet Error Categories 8.7.2 Bus Turn-around Timing Table 8-8 – Packet Error Types
251	8.7.3 False EOPs Figure 8-49 – Bus Turn-around Timer Usage
252	8.7.4 Babble and Loss of Activity Recovery
253	9 Chapter 9 USB Device Framework 9.1 USB Device States 9.1.1 Visible Device States
254	Figure 9-1 – Device State Diagram
255	Table 9-1 – Visible Device States
257	9.1.2 Bus Enumeration 9.2 Generic USB Device Operations
258	9.2.1 Dynamic Attachment and Removal 9.2.2 Address Assignment 9.2.3 Configuration
259	9.2.4 Data Transfer 9.2.5 Power Management 9.2.6 Request Processing
261	9.2.7 Request Error
262	9.3 USB Device Requests 9.3.1 bmRequestType 9.3.2 bRequest 9.3.3 wValue Table 9-2 – Format of Setup Data
263	9.3.4 wIndex 9.3.5 wLength 9.4 Standard Device Requests Figure 9-2 – wIndex Format when Specifying an Endpoint Figure 9-3 – wIndex Format when Specifying an Interface
264	Table 9-3 – Standard Device Requests Table 9-4 – Standard Request Codes
265	9.4.1 Clear Feature Table 9-5 – Descriptor Types Table 9-6 – Standard Feature Selectors
266	9.4.2 Get Configuration 9.4.3 Get Descriptor
267	9.4.4 Get Interface 9.4.5 Get Status
268	Figure 9-4 – Information Returned by a GetStatus() Request to a Device Figure 9-5 – Information Returned by a GetStatus() Request to an Interface Figure 9-6 – Information Returned by a GetStatus() Request to an Endpoint
269	9.4.6 Set Address 9.4.7 Set Configuration
270	9.4.8 Set Descriptor
271	9.4.9 Set Feature Table 9-7 – Test Mode Selectors
272	9.4.10 Set Interface 9.4.11 Synch Frame
273	9.5 Descriptors 9.6 Standard USB Descriptor Definitions 9.6.1 Device
274	Table 9-8 – Standard Device Descriptor
275	9.6.2 Device_Qualifier
276	9.6.3 Configuration Table 9-9 – Device_Qualifier Descriptor
277	Table 9-10 – Standard Configuration Descriptor
278	9.6.4 Other_Speed_Configuration 9.6.5 Interface Table 9-11 – Other_Speed_Configuration Descriptor
279	9.6.6 Endpoint Table 9-12 – Standard Interface Descriptor
280	Table 9-13 – Standard Endpoint Descriptor
281	Table 9-13 – Standard Endpoint Descriptor (Continued)
282	9.6.7 String Figure 9-7 – Example of Feedback Endpoint Numbers Figure 9-8 – Example of Feedback Endpoint Relationships Table 9-14 – Allowed wMaxPacketSize Values for Different Numbers of Transactions per Microframe
283	9.7 Device Class Definitions 9.7.1 Descriptors 9.7.2 Interface(s) and Endpoint Usage Table 9-15 – String Descriptor Zero, Specifying Languages Supported by the Device Table 9-16 – UNICODE String Descriptor
284	9.7.3 Requests
285	10 Chapter 10 USB Host: Hardware and Software 10.1 Overview of the USB Host 10.1.1 Overview Figure 10-1 – Interlayer Communications Model
286	Figure 10-2 – Host Communications
288	10.1.2 Control Mechanisms 10.1.3 Data Flow
289	10.1.4 Collecting Status and Activity Statistics 10.1.5 Electrical Interface Considerations 10.2 Host Controller Requirements
290	10.2.1 State Handling 10.2.2 Serializer/Deserializer 10.2.3 Frame and Microframe Generation Figure 10-3 – Frame and Microframe Creation
291	10.2.4 Data Processing 10.2.5 Protocol Engine 10.2.6 Transmission Error Handling
292	10.2.7 Remote Wakeup 10.2.8 Root Hub 10.2.9 Host System Interface 10.3 Overview of Software Mechanisms
293	10.3.1 Device Configuration Figure 10-4 – Configuration Interactions
295	10.3.2 Resource Management 10.3.3 Data Transfers
296	10.3.4 Common Data Definitions 10.4 Host Controller Driver
297	10.5 Universal Serial Bus Driver 10.5.1 USBD Overview
298	Figure 10-5 – Universal Serial Bus Driver Structure
299	10.5.2 USBD Command Mechanism Requirements
301	10.5.3 USBD Pipe Mechanisms
303	10.5.4 Managing the USB via the USBD Mechanisms
305	10.5.5 Passing USB Preboot Control to the Operating System 10.6 Operating System Environment Guides
306	11 Chapter 11 Hub Specification 11.1 Overview 11.1.1 Hub Architecture
307	11.1.2 Hub Connectivity Figure 11-1 – Hub Architecture
308	Figure 11-2 – Hub Signaling Connectivity Figure 11-3 – Resume Connectivity
309	11.2 Hub Frame/Microframe Timer 11.2.1 High-speed Microframe Timer Range 11.2.2 Full-speed Frame Timer Range Table 11-1 – High-speed Microframe Timer Range Contributions
310	11.2.3 Frame/Microframe Timer Synchronization Table 11-2 – Full-speed Frame Timer Range Contributions
311	Figure 11-4 – Example High-speed EOF Offsets Due to Propagation Delay Without EOF Advancement Figure 11-5 – Example High-speed EOF Offsets Due to Propagation Delay With EOF Advancement
312	11.2.4 Microframe Jitter Related to Frame Jitter 11.2.5 EOF1 and EOF2 Timing Points Table 11-3 – Hub and Host EOF1/EOF2 Timing Points
313	Figure 11-6 – High-speed EOF2 Timing Point Figure 11-7 – High-speed EOF1 Timing Point Figure 11-8 – Full-speed EOF Timing Points
315	11.3 Host Behavior at End-of-Frame 11.3.1 Full-/low-speed Latest Host Packet 11.3.2 Full-/low-speed Packet Nullification
316	11.3.3 Full-/low-speed Transaction Completion Prediction 11.4 Internal Port
317	11.4.1 Inactive 11.4.2 Suspend Delay 11.4.3 Full Suspend (Fsus) 11.4.4 Generate Resume (GResume) Figure 11-9 – Internal Port State Machine Table 11-4 – Internal Port Signal/Event Definitions
318	11.5 Downstream Facing Ports
319	Figure 11-10 – Downstream Facing Hub Port State Machine
320	11.5.1 Downstream Facing Port State Descriptions Table 11-5 – Downstream Facing Port Signal/Event Definitions
324	11.5.2 Disconnect Detect Timer
325	11.5.3 Port Indicator
326	Figure 11-11 – Port Indicator State Diagram Table 11-6 – Automatic Port State to Port Indicator Color Mapping
327	11.6 Upstream Facing Port 11.6.1 Full-speed Table 11-7 – Port Indicator Color Definitions
328	11.6.2 High-speed 11.6.3 Receiver Figure 11-12 – Upstream Facing Port Receiver State Machine
329	Table 11-8 – Upstream Facing Port Receiver Signal/Event Definitions
331	11.6.4 Transmitter Figure 11-13 – Upstream Facing Port Transmitter State Machine
332	Table 11-9 – Upstream Facing Port Transmit Signal/Event Definitions
333	11.7 Hub Repeater 11.7.1 High-speed Packet Connectivity Figure 11-14 – Example Hub Repeater Organization
334	Figure 11-15 – High-speed Port Selector State Machine
335	11.7.2 Hub Repeater State Machine Table 11-10 – High-speed Port Selector Signal/Event Definitions
336	Figure 11-16 – Hub Repeater State Machine Table 11-11 – Hub Repeater Signal/Event Definitions
337	11.7.3 Wait for Start of Packet from Upstream Port (WFSOPFU) 11.7.4 Wait for End of Packet from Upstream Port (WFEOPFU) 11.7.5 Wait for Start of Packet (WFSOP) 11.7.6 Wait for End of Packet (WFEOP)
338	11.8 Bus State Evaluation 11.8.1 Port Error 11.8.2 Speed Detection
339	11.8.3 Collision 11.8.4 Low-speed Port Behavior
340	11.9 Suspend and Resume
341	Figure 11-17 – Example Remote-wakeup Resume Signaling With Full-/low-speed Device Figure 11-18 – Example Remote-wakeup Resume Signaling With High-speed Device
342	11.10 Hub Reset Behavior 11.11 Hub Port Power Control
343	11.11.1 Multiple Gangs 11.12 Hub Controller
344	11.12.1 Endpoint Organization 11.12.2 Hub Information Architecture and Operation Figure 11-19 – Example Hub Controller Organization
345	11.12.3 Port Change Information Processing Figure 11-20 – Relationship of Status, Status Change,and Control Information to Device States
346	11.12.4 Hub and Port Status Change Bitmap Figure 11-21 – Port Status Handling Method
347	11.12.5 Over-current Reporting and Recovery Figure 11-22 – Hub and Port Status Change Bitmap Figure 11-23 – Example Hub and Port Change Bit Sampling
348	11.12.6 Enumeration Handling 11.13 Hub Configuration
349	11.14 Transaction Translator Table 11-12 – Hub Power Operating Mode Summary
350	11.14.1 Overview Figure 11-24 – Transaction Translator Overview
351	Figure 11-25 – Periodic and Non-periodic Buffer Sections of TT
352	11.14.2 Transaction Translator Scheduling Figure 11-26 – TT Microframe Pipeline for Periodic Split Transactions
353	Figure 11-27 – TT Nonperiodic Buffering
354	11.15 Split Transaction Notation Information Figure 11-28 – Example Full-/low-speed Handler Scheduling for Start-splits Figure 11-29 – Flow Sequence Legend
355	Figure 11-30 – Legend for State Machines
357	11.16 Common Split Transaction State Machines Figure 11-31 – State Machine Context Overview Figure 11-32 – Host Controller Split Transaction State Machine Hierarchy Overview
358	11.16.1 Host Controller State Machine Figure 11-33 – Transaction Translator State Machine Hierarchy Overview Figure 11-34 – Host Controller
359	Figure 11-35 – HC_Process_Command
360	Figure 11-36 – HC_Do_Start
361	Figure 11-37 – HC_Do_Complete
362	11.16.2 Transaction Translator State Machine Figure 11-38 – Transaction Translator
363	Figure 11-39 – TT_Process_Packet
364	Figure 11-40 – TT_Do_Start
365	Figure 11-41 – TT_Do_Complete Figure 11-42 – TT_BulkSS
366	Figure 11-43 – TT_BulkCS Figure 11-44 – TT_IntSS
367	11.17 Bulk/Control Transaction Translation Overview Figure 11-45 – TT_IntCS Figure 11-46 – TT_IsochSS
368	11.17.1 Bulk/Control Split Transaction Sequences
369	Figure 11-47 – Sample Algorithm for Compare_buffs
370	Figure 11-48 – Bulk/Control OUT Start-split Transaction Sequence
371	Figure 11-49 – Bulk/Control OUT Complete-split Transaction Sequence
372	Figure 11-50 – Bulk/Control IN Start-split Transaction Sequence
373	Figure 11-51 – Bulk/Control IN Complete-split Transaction Sequence
374	11.17.2 Bulk/Control Split Transaction State Machines Figure 11-52 – Bulk/Control OUT Start-split Transaction Host State Machine
375	Figure 11-53 – Bulk/Control OUT Complete-split Transaction Host State Machine
376	Figure 11-54 – Bulk/Control OUT Start-split Transaction TT State Machine Figure 11-55 – Bulk/Control OUT Complete-split Transaction TT State Machine
377	Figure 11-56 – Bulk/Control IN Start-split Transaction Host State Machine
378	Figure 11-57 – Bulk/Control IN Complete-split Transaction Host State Machine
379	11.17.3 Bulk/Control Sequencing Figure 11-58 – Bulk/Control IN Start-split Transaction TT State Machine Figure 11-59 – Bulk/Control IN Complete-split Transaction TT State Machine
380	11.17.4 Bulk/Control Buffering Requirements 11.17.5 Other Bulk/Control Details 11.18 Periodic Split Transaction Pipelining and Buffer Management
381	11.18.1 Best Case Full-Speed Budget 11.18.2 TT Microframe Pipeline Figure 11-60 – Best Case Budgeted Full-speed Wire Time With No Bit Stuffing
382	11.18.3 Generation of Full-speed Frames 11.18.4 Host Split Transaction Scheduling Requirements Figure 11-61 – Scheduling of TT Microframe Pipeline
383	Figure 11-62 – Isochronous OUT Example That Avoids a Start-split-end With Zero Data
384	Figure 11-63 – End of Frame TT Pipeline Scheduling Example Figure 11-64 – Isochronous IN Complete-split Schedule Example at L=Y6
385	11.18.5 TT Response Generation Figure 11-65 – Isochronous IN Complete-split Schedule Example at L=Y7
386	11.18.6 TT Periodic Transaction Handling Requirements
388	11.18.7 TT Transaction Tracking Figure 11-66 – Microframe Pipeline
389	11.18.8 TT Complete-split Transaction State Searching Figure 11-67 – Advance_Pipeline Pseudocode
390	11.19 Approximate TT Buffer Space Required 11.20 Interrupt Transaction Translation Overview
391	11.20.1 Interrupt Split Transaction Sequences Figure 11-68 – Interrupt OUT Start-split Transaction Sequence
392	Figure 11-69 – Interrupt OUT Complete-split Transaction Sequence Figure 11-70 – Interrupt IN Start-split Transaction Sequence
393	Figure 11-71 – Interrupt IN Complete-split Transaction Sequence
394	11.20.2 Interrupt Split Transaction State Machines Figure 11-72 – Interrupt OUT Start-split Transaction Host State Machine
395	Figure 11-73 – Interrupt OUT Complete-split Transaction Host State Machine
396	Figure 11-74 – Interrupt OUT Start-split Transaction TT State Machine Figure 11-75 – Interrupt OUT Complete-split Transaction TT State Machine
397	Figure 11-76 – Interrupt IN Start-split Transaction Host State Machine
398	Figure 11-77 – Interrupt IN Complete-split Transaction Host State Machine
399	Figure 11-78 – HC_Data_or_Error State Machine Figure 11-79 – Interrupt IN Start-split Transaction TT State Machine
400	11.20.3 Interrupt OUT Sequencing Figure 11-80 – Interrupt IN Complete-split Transaction TT State Machine
401	11.20.4 Interrupt IN Sequencing Figure 11-81 – Example of CRC16 Handling for Interrupt OUT
402	11.21 Isochronous Transaction Translation Overview Figure 11-82 – Example of CRC16 Handling for Interrupt IN
403	11.21.1 Isochronous Split Transaction Sequences
404	Figure 11-83 – Isochronous OUT Start-split Transaction Sequence Figure 11-84 – Isochronous IN Start-split Transaction Sequence
405	Figure 11-85 – Isochronous IN Complete-split Transaction Sequence
406	11.21.2 Isochronous Split Transaction State Machines Figure 11-86 – Isochronous OUT Start-split Transaction Host State Machine
407	Figure 11-87 – Isochronous OUT Start-split Transaction TT State Machine
408	Figure 11-88 – Isochronous IN Start-split Transaction Host State Machine Figure 11-89 – Isochronous IN Complete-split Transaction Host State Machine
409	11.21.3 Isochronous OUT Sequencing Figure 11-90 – Isochronous IN Start-split Transaction TT State Machine Figure 11-91 – Isochronous IN Complete-split Transaction TT State Machine
410	11.21.4 Isochronous IN Sequencing Figure 11-92 – Example of CRC16 Isochronous OUT Data Packet Handling
411	11.22 TT Error Handling 11.22.1 Loss of TT Synchronization With HS SOFs Figure 11-93 – Example of CRC16 Isochronous IN Data Packet Handling
412	11.22.2 TT Frame and Microframe Timer Synchronization Requirements
413	11.23 Descriptors Figure 11-94 – Example Frame/Microframe Synchronization Events
414	11.23.1 Standard Descriptors for Hub Class
422	11.23.2 Class-specific Descriptors Table 11-13 – Hub Descriptor
423	11.24 Requests 11.24.1 Standard Requests Table 11-14 – Hub Responses to Standard Device Requests
424	11.24.2 Class-specific Requests Table 11-15 – Hub Class Requests
425	Table 11-16 – Hub Class Request Codes Table 11-17 – Hub Class Feature Selectors
427	Table 11-18 – wValue Field for Clear_TT_Buffer
428	Table 11-19 – Hub Status Field, wHubStatus
429	Table 11-20 – Hub Change Field, wHubChange
430	Table 11-21 – Port Status Field, wPortStatus
434	Table 11-22 – Port Change Field, wPortChange
435	Table 11-23 – Format of Returned TT State
439	Table 11-24 – Test Mode Selector Codes Table 11-25 – Port Indicator Selector Codes
440	Appendix A Transaction Examples A.1 Bulk/Control OUT and SETUP Transaction Examples
441	Figure A-1 – Normal No Smash
442	Figure A-2 – Normal HS DATA0/1 Smash
443	Figure A-3 – Normal HS DATA0/1 3 Strikes Smash
444	Figure A-4 – Normal HS ACK(S) Smash (case 1)
445	Figure A-5 – Normal HS ACK(S) Smash (case 2)
446	Figure A-6 – Normal HS ACK(S) 3 Strikes Smash
447	Figure A-7 – Normal HS CSPLIT Smash
448	Figure A-8 – Normal HS CSPLIT 3 Strikes Smash
449	Figure A-9 – Normal HS ACK(C) Smash
450	Figure A-10 – Normal S ACK(C) 3 Strikes Smash
451	Figure A-11 – Normal FS/LS DATA0/1 Smash
452	Figure A-12 – Normal FS/LS DATA0/1 3 Strikes Smash
453	Figure A-13 – Normal FS/LS ACK Smash
454	Figure A-14 – Normal FS/LS ACK 3 Strikes Smash
455	Figure A-15 – No buffer Available No Smash (HS NAK(S))
456	Figure A-16 – No Buffer Available HS NAK(S) Smash
457	Figure A-17 – No Buffer Available HS NAK(S) 3 Strikes Smash
458	Figure A-18 – CS Earlier No Smash (HS NYET)
459	Figure A-19 – CS Earlier HS NYET Smash (case 1)
460	Figure A-20 – CS Earlier HS NYET Smash (case 2)
461	Figure A-21 – CS Earlier HS NYET 3 Strikes Smash
462	Figure A-22 – Device Busy No Smash(FS/LS NAK)
463	Figure A-23 – Device Stall No Smash(FS/LS STALL)
464	A.2 Bulk/Control IN Transaction Examples
465	Figure A-24 – Normal No Smash
466	Figure A-25 – Normal HS SSPLIT Smash
467	Figure A-26 – Normal SSPLIT 3 Strikes Smash
468	Figure A-27 – Normal HS ACK(S) Smash (case 1)
469	Figure A-28 – Normal HS ACK(S) Smash (case 2)
470	Figure A-29 – Normal HS ACK(S) 3 Strikes Smash
471	Figure A-30 – Normal HS CSPLIT Smash
472	Figure A-31 – Normal HS CSPLIT 3 Strikes Smash
473	Figure A-32 – Normal HS DATA0/1 Smash
474	Figure A-33 – Normal HS DATA0/1 3 Strikes Smash
475	Figure A-34 – Normal FS/LS IN Smash
476	Figure A-35 – Normal FS/LS IN 3 Strikes Smash
477	Figure A-36 – Normal FS/LS DATA0/1 Smash
478	Figure A-37 – Normal FS/LS DATA0/1 3 Strikes Smash
479	Figure A-38 – Normal FS/LS ACK Smash
480	Figure A-39 – No Buffer Available No Smash(HS NAK(S))
481	Figure A-40 – No Buffer Available HS NAK(S) Smash
482	Figure A-41 – No Buffer Available HS NAK(S) 3 Strikes Smash
483	Figure A-42 – CS Earlier No Smash (HS NYET)
484	Figure A-43 – CS Earlier HS NYET Smash (case 1)
485	Figure A-44 – CS Earlier HS NYET Smash (case 2)
486	Figure A-45 – Device Busy No Smash(FS/LS NAK)
487	Figure A-46 – Device Stall No Smash(FS/LS STALL)
488	A.3 Interrupt OUT Transaction Examples
490	Figure A-47 – Normal No Smash(FS/LS Handshake Packet is Done by M+1)
491	Figure A-48 – Normal HS DATA0/1 Smash
492	Figure A-49 – Normal HS CSPLIT Smash
493	Figure A-50 – Normal HS CSPLIT 3 Strikes Smash
494	Figure A-51 – Normal HS ACK(C) Smash
495	Figure A-52 – Normal HS ACK(C) 3 Strikes Smash
496	Figure A-53 – Normal FS/LS DATA0/1 Smash
497	Figure A-54 – Normal FS/LS ACK Smash
498	Figure A-55 – Searching No Smash
499	Figure A-56 – CS Earlier No Smash(HS NYET and FS/LS Handshake Packet is Done by M+2)
500	Figure A-57 – CS Earlier No Smash(HS NYET and FS/LS Handshake Packet is Done by M+3)
501	Figure A-58 – CS Earlier HS NYET Smash
502	Figure A-59 – CS Earlier HS NYET 3 Strikes Smash
503	Figure A-60 – Abort and Free Abort(FS/LS Transaction is Continued at End of M+3)
504	Figure A-61 – Abort and Free Free(FS/LS Transaction is not Started at End of M+3)
505	Figure A-62 – Device Busy No Smash(FS/LS NAK)
506	Figure A-63 – Device Stall No Smash(FS/LS STALL)
507	A.4 Interrupt IN Transaction Examples
509	Figure A-64 – Normal No Smash (FS/LS Data Packet is on M+1)
510	Figure A-65 – Normal HS SSPLIT Smash
511	Figure A-66 – Normal HS CSPLIT Smash
512	Figure A-67 – Normal HS CSPLIT 3 Strikes Smash
513	Figure A-68 – Normal HS DATA0/1 Smash
514	Figure A-69 – Normal HS DATA0/1 3 Strikes Smash
515	Figure A-70 – Normal FS/LS IN Smash
516	Figure A-71 – Normal FS/LS DATA0/1 Smash
517	Figure A-72 – Normal FS/LS ACK Smash
518	Figure A-73 – Searching No Smash
519	Figure A-74 – CS Earlier No Smash (HS MDATA and FS/LS Data Packet is on M+1 and M+2)
520	Figure A-75 – CS Earlier No Smash (HS NYET and FS/LS Data Packet is on M+2)
521	Figure A-76 – CS Earlier No Smash (HS NYET and MDATA and FS/LS Data Packet is on M+2 and M+3)
522	Figure A-77 – CS Earlier No Smash(HS NYET and FS/LS Data Packet is on M+3)
523	Figure A-78 – CS Earlier HS NYET Smash
524	Figure A-79 – CS Earlier HS NYET 3 Strikes Smash
525	Figure A-80 – Abort and Free Abort (HS NYET and FS/LS Transaction is Continued at End of M+3)
526	Figure A-81 – Abort and Free Free (HS NYET and FS/LS Transaction is not Started at End of M+3)
527	Figure A-82 – Device Busy No Smash(FS/LS NAK)
528	Figure A-83 – Device Stall No Smash(FS/LS STALL)
529	A.5 Isochronous OUT Split-transaction Examples
538	A.6 Isochronous IN Split-transaction Examples
552	Appendix B Example Declarations for State Machines
553	B.1 Global Declarations
556	B.2 Host Controller Declarations
558	B.3 Transaction Translator Declarations
562	Appendix C Reset Protocol State Diagrams C.1 Downstream Facing Port State Diagram
563	Figure C-1 – Downstream Facing Port Reset Protocol State Diagram
564	C.2 Upstream Facing Port State Diagram C.2.1 Reset From Suspended State
565	Figure C-2 – Upstream Facing Port Reset Detection State Diagram
566	Figure C-3 – Upstream Facing Port Reset Handshake State Diagram
567	C.2.2 Reset From Full-speed Non-suspended State C.2.3 Reset From High-speed Non-suspended State C.2.4 Reset Handshake
639	Table 5-3 – High-speed Control Transfer Limits
640	Table 5-8 – High-speed Interrupt Transaction Limits
641	Table 5-5 – High-speed Isochronous Transaction Limits
646	Figure 8-27 – Host High-speed Bulk OUT/Control Ping State Machine
647	Figure 8-31 – FS Bulk, FS/LS/ Control, or HS/FS/LS Interrupt/ OUT Transaction Host State Machine
648	Figure 8-32 – FS Bulk, /FS/LS Control, /or HS/FS/LSInterrupt OUT Transaction Host State Machine
650	Table 9-3 – Standard Device Requests
664	Figure11-11 – Port Indicator State Diagram
666	Table 11-14 – Hub Responses to Standard Device Requests
668	Table 11-21 – Port Status Field, wPortStatus
673	Figure 6-1 – Keyed Connector Protocol
675	Figure 6-2 – USB Standard Detachable Cable Assembly
676	Figure 6-3 – USB Standard Mini-connector Detachable Cable Assembly
678	Figure 6-3 – USB High-/full-speed Hardwired Cable Assembly
680	Figure 6-46-5 – USB Low-speed Hardwired Cable Assembly
682	Figure 6-56-6 – USB Icon
683	Figure 6-66-7 – Typical USB Plug Orientation
684	Figure 6-8 – Typical USB “Mini-B” Connector Plug Orientation
685	Table 6-1 – USB Series “A” and Series “B” Connector Termination Assignment Table 6-2 – USB Series “mini-B” Connector Termination Assignment
686	Figure 6-76-9 – USB Series “A” Receptacle Interface and Mating Drawing
687	Figure 6-86-10 – USB Series “B” Receptacle Interface and Mating Drawing
688	Figure 6-11 – USB Series “Mini-B” Receptacle Interface and Mating Drawing
689	Figure 6-12 – USB Series “Mini-B” Receptacle Interface Drawing (Detail).tiff
692	Figure 6-96-13 – USB Series “A” Plug Interface Drawing
693	Figure 6-106-14 – USB Series “B” Plug Interface Drawing
694	Figure 6-15 – USB Series “Mini-B” Plug Interface Drawing
697	Figure 6-116-16 – Typical High-/full-speed Cable Construction
698	Table 6-26-3 – Power Pair Table 6-36-4 – Signal Pair
699	Table 6-46-5 – Drain Wire Signal Pair
700	Table 6-56-6 – Nominal Cable Diameter Table 6-66-7 – Conductor Resistance
701	Table 6-76-8 – USB Electrical, Mechanical, and Environmental Compliance Standards
702	Table 6-76-8 – USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
703	Table 6-76-8 – USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
704	Table 6-76-8– USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
705	Table 6-76-8– USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
707	Figure 6-126-17 – Single Pin-type Series “A” Receptacle
708	Figure 6-136-18 – Dual Pin-type Series “A” Receptacle
709	Figure 6-146-19 – Single Pin-type Series “B” Receptacle
710	Figure 6-20 – Single Pin-Type Series “Mini-B” Receptacle
720	Table 9-13 – Standard Endpoint Descriptor (Continued)
722	Table 11-6 – Automatic Port State to Port Indicator Color Mapping
723	Figure 11-11 – Port Indicator State Diagram
728	Figure 11-82 – Example of CRC16 Handling for Interrupt IN Figure 11-93 – Example of CRC16 Isochronous IN Data Packet Handling
736	Table 9-5 – Descriptor Types
737	Table 9-13 – Standard Interface Association Descriptor Table 9-1314 – Standard Endpoint Descriptor
739	Figure 6-15 – USB Series “Mini-B” Plug Interface Drawing (1 of 2)
740	Figure 6-15 – USB Series “Mini-B” Plug Interface Drawing (2 of 2)
743	Table 9-16 – UNICODE String Descriptor
746	Table 1-1 – USB Link Power Management (Lx) States
747	Figure 1-1 – LPM State Transition Diagram Table 1-2 – Summary Similarities/Differences Between L1 and L2
748	Table 2-1 – PID Types
749	Figure 2-1 – Packets in an Extension Token Transaction
750	Figure 2-2 – LPM Extended Token Table 2-2 – SubPID Types Table 2-2 – SubPID Types (cont.)
751	Figure 2-3 – LPM Transaction Format Table 2-3 – LPM Token bmAttributes Field Definition
752	Table 3-1 – USB Device Capabilities – USB 2.0 Extension Descriptor
753	Table 3-1 – USB Device Capabilities – USB 2.0 Extension Descriptor (cont.)
754	Figure 4-1 – Port Control Model for Transitioning a Port to L1
755	Figure 4-2 – LPM Transaction and Transition Timing to L1
756	Figure 4-3 – Device Initiated L1 to L0 Transition (Remote Wake)
757	Figure 4-4 – Example Remote-wakeup L1 Exit with Full-speed DeviceUnder Connected Hub
759	Table 4-1 – Device Initiated Resume Propagation and Adjacent Port Side-effects
760	Figure 4-5 – Basic Port Control Model for Transitioning a Port out of L1 Figure 4-6 – Host Initiated L1 to L0 Transition (L1 Exit)
761	Figure 4-7 – USB 2.0 Hub Reference Port State Machine Relationships with L1 Additions
762	Figure 4-8 – L1 Addendum to the Upstream Facing Port Receiver State Machine Table 4-2 – Upstream Facing Port Receiver Signal/Event Definitions (Addendum)
764	Figure 4-9 – Addendum to the Upstream Facing Port Transmitter State Machine Table 4-3 – Upstream Facing Port Transmitter Signal/Event Definitions (Addendum)
765	Figure 4-10 – Addendum to the Internal Port State Machine
766	Table 4-4 – Internal Port Signal/Event Definitions (Addendum)
767	Figure 4-11 – Addendum to Downstream Facing Hub Port State Machine Table 4-5 – Downstream Port Signal/Event Definitions (Addendum)
770	Table 4-6 – Summary LPM Timing Characteristics Table 4-7 – Hub Class Feature Selectors
771	Table 4-7 – Hub Class Feature Selectors (cont.) Table 4-8 – wIndex Definition for Clear Port Feature on an LPM Enabled Hub
772	Table 4-9 – Port Status Bits with L1 Additions
773	Table 4-10 – Port Change Bits with L1 Additions
774	Table 4-11 – Set and Test Port Feature Details
789	Figure 7-29 – Connect Event Timing

Published By	Publication Date	Number of Pages
BSI	2016	796


PDF Format	Searchable	Printable	Preview Now

Status	Definitive
Pages	796
Publication Date	2016-02-29
ISBN	978 0 580 88004 9
Standard Number	BS EN 62680-2-1:2015
Title	Universal Serial Bus interfaces for data and power – Universal Serial Bus Specification, Revision 2.0 (TA 14)
Identical National Standard Of	IEC 62680-2-1:2015, EN 62680-2-1:2015, EN 61158-6-10:2008
Descriptors	Battery chargers, Electronic equipment and components, Electric plugs, Audio equipment, Battery-powered devices, Identification methods, Electrical properties and phenomena, Portable, Electric connectors, Multimedia, Electric charge, Dimensions, Voltage
Publisher	BSI
Committee	EPL/100
ICS Codes	33.120.20 - Wires and symmetrical cables

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