IEEE 1285-2005

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IEEE Standard for Scalable Storage Interface

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IEEE	2005

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Description

New IEEE Standard – Active. This document specifies a scalable interface between mass-storage devices and controlling hard-ware/software. The interface has been optimized for low-latency interconnects, assuming that the proces-sor/controller and the storage device can often be co-located on the same printed-circuit board. The interface can also be used with longer-distance bus-like interconnects, including (but not limited to) IEEE Std 1394-1995 Serial Bus and IEEE Std 1596-1992 Scalable Coherent Interface.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Standard for Scalable Storage Interface (S2I)
3	Title page
5	Introduction Notice to users
6	Participants
7	CONTENTS
9	1. Overview 1.1 Scope 1.2 Purpose 1.3 Background
10	1.4 Scalable storage interface properties 1.5 Historical perspective
11	1.6 Non-storage applications
12	1.7 S2I command execution 1.7.1 Shared command and status queues
13	1.7.2 Command capabilities
14	1.7.3 S2I capabilities 1.8 S2I topologies 1.8.1 Alpha-level interface
15	1.8.2 Delta-level interfaces
16	1.8.3 Multi-level RAID controllers
17	1.9 S2I interconnects 1.9.1 Interconnect capabilities 1.10 Memory-mapped addresses
18	1.11 Shared memory-mapped registers
19	2. Normative references
20	3. Glossary and notation 3.1 Definitions 3.1.1 Conformance levels 3.1.2 Definitions of S2I related terms
23	3.2 Field names 3.3 C-code notation
24	3.4 Bit and byte ordering 3.4.1 Endian ordering options
25	3.4.2 Big-endian byte ordering
26	3.4.3 Little-endian alternatives 3.5 Generic delta-level command lists 3.6 Data formats 3.6.1 Numerical values
27	3.6.2 Reserved registers and fields
28	4. Abbreviations and acronyms
29	5. Alpha-level interface 5.1 Alpha-level overview 5.1.1 Alpha-level distinctions 5.1.2 Alpha-level components
30	5.1.3 Alpha-level memory-mapped addresses 5.1.4 Buffer block access 5.2 Command execution
31	5.2.1 Command-list additions 5.2.2 Out-of-order command execution 5.3 Alpha4 command and status entries 5.3.1 command entry format
32	5.3.2 status-entry format
33	5.4 Alpha8 command and status entries 5.4.1 Extended command entry format
34	5.4.2 status-entry format 5.5 Command processing
35	5.6 Alpha-level CSRs 5.6.1 Alpha-level CSR offset addresses 5.6.2 control register
36	5.6.3 state register 5.6.4 Operational states
38	6. Delta interface properties 6.1 Delta-level distinctions 6.2 Delta-level memory-mapped addresses
39	6.2.1 Mover operations 6.2.2 Mover register addresses
40	6.2.3 Device-buffer addressing 6.3 Address formats 6.3.1 Delta16/Delta32 address formats
41	6.3.2 Delta64 address formats 6.3.3 Address modes
42	6.4 Command lists 6.4.1 Command list structure 6.4.2 Command prefetching 6.4.3 Command activation
45	6.5 Legacy command-set support 6.6 Delta-level command processing 6.6.1 Delta-level command blocks
47	6.6.2 Common delta-level command values
48	6.6.3 Data transfer locations
49	6.7 Command sequence ordering
50	6.8 Input/output transfers 6.8.1 Device space selections 6.8.2 Read/write transfers
51	6.9 Scatter/gather transfers 6.9.1 Scattered system addresses 6.9.2 Scatter/gather lists
52	6.10 System-bus transactions 6.10.1 Read/write transaction usage 6.10.2 Transaction requirements
53	6.10.3 Transaction ordering 6.10.4 Idempotent transactions
54	6.11 Status reports 6.11.1 Mailbox status reports
55	6.11.2 Adjacent status reports 6.11.3 Status report writes
56	6.11.4 Interrupt indications 6.12 Command synchronization
57	6.12.1 Synchronized device-to-device transfers 6.12.2 Synchronized DMA transfers
58	6.13 Error conditions 6.13.1 Fatal access errors 6.13.2 Cancelled commands
59	6.14 Delta-level mover CSRs 6.14.1 CSR address offsets 6.14.2 wakeup register
60	6.14.3 flags register 6.14.4 state register
61	6.14.5 control register
62	6.15 Operational mover states 6.15.1 Basic operational states 6.15.2 Optional operational states
63	6.15.3 Flushing input buffers
64	7. Delta interfaces 7.1 Delta16 overview 7.1.1 Delta16 distinctions 7.1.2 Command lists
65	7.1.3 Delta16 command values
66	7.1.4 Delta16 command entry formats
73	7.1.5 Delta16 Mover CSRs
75	7.2 Delta32 overview 7.2.1 Delta32 distinctions
76	7.2.2 Delta32 command values
77	7.2.3 Delta32 command entry formats
83	7.3 Delta32 Mover CSRs 7.3.1 CSR address offsets
84	7.4 Delta64 overview 7.4.1 Delta64 distinctions 7.4.2 Delta64 commands
85	7.4.3 Delta64 command entry formats
91	7.4.4 Delta64 CSR address offsets
92	7.4.5 nextCommand register
93	Annex A (informative) Bibliography
94	Annex B (informative) Illustrative applications B.1 Secure logins
95	B.2 Scattered buffer allocation B.2.1 Dynamic network-packet storage allocation B.2.2 Saving sense (extended status) information
96	B.3 Heartbeat timers B.4 Event reports B.5 Power-level management
97	B.6 Timed command execution B.6.1 Extended MoverCsr.state register B.6.2 timeLimit register
98	B.7 DiskLite architecture B.7.1 Media space partitioning
99	B.7.2 Supported features
100	B.7.3 Information space addresses
101	Annex C (informative) Software based RAID C.1 RAID I/O driver software C.2 Single-block OUTPUT
103	C.3 Striped-block OUTPUT
104	C.4 Erasure-correcting single-block INPUT
105	C.5 Erasure-correcting multiple-block INPUT
106	Annex D (informative) Physical interface possibilities D.1 Delta16-level backplane interface D.1.1 Direct unit addressing
107	D.1.2 Hardwired interrupts D.2 Delta64 Serial Bus interface
108	D.2.1 Serial Bus addressing D.2.2 Delta64 addresses
109	D.2.3 Dependent fields
111	Annex E (informative) C-code illustrations