{"id":460324,"date":"2024-10-20T10:09:07","date_gmt":"2024-10-20T10:09:07","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bsi-24-30489409-dc-2024\/"},"modified":"2024-10-26T18:46:07","modified_gmt":"2024-10-26T18:46:07","slug":"bsi-24-30489409-dc-2024","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bsi-24-30489409-dc-2024\/","title":{"rendered":"BSI 24\/30489409 DC 2024"},"content":{"rendered":"
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | 30489409-NC.pdf <\/td>\n<\/tr>\n | ||||||
3<\/td>\n | 100_4131e_CDV.pdf <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 1 General Description 1.1 Introduction 1.1.1 Scope 1.1.2 Document organization 1.1.3 Design goals <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 1.1.4 BPP and MPP interoperability 1.1.5 Related documents <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 1.2 Architectural overview 1.2.1 System Description <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 1.2.2 System block diagrams <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 1.3 Glossary 1.3.1 Definitions <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | 1.3.2 Acronyms 1.3.3 Symbols <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 1.4 System Model vs Spec <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 2 Authentication Protocol 2.1 Authentication <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 3 Coil Design 3.1 Introduction and Background 3.2 PTx Coil System Model 3.2.1 Mechanical Construction 3.2.1.1 Overview <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 3.2.1.2 Top Enclosure 3.2.1.3 Coil Module (AC magnetics) <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 3.2.1.4 Coil Module (permanent magnets) <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | 3.2.1.5 Magnet shunt top view <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 3.2.1.6 Bottom enclosure <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 3.2.1.7 Top view of bottom enclosure <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 3.2.1.8 Overall Assembly 3.2.1.9 PTx Orientation Magnets 3.2.1.9.1 Transmitter-side Orientation Magnet <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 3.2.2 Electrical Properties 3.2.2.1 Electrical Parameters of PTx coil system model <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 3.2.2.2 Preventing Saturation of PRx Shielding <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | 3.3 PRx Coil System Model 3.3.1 Mechanical Construction 3.3.1.1 Overall Assembly <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | 3.3.1.2 Bottom Enclosure 3.3.1.3 Support Plate 3.3.1.4 Coil Module <\/td>\n<\/tr>\n | ||||||
43<\/td>\n | 3.3.1.5 Coil Module (permanent magnets) <\/td>\n<\/tr>\n | ||||||
45<\/td>\n | 3.3.1.6 Friendly Metal Block 3.3.1.7 Overall Assembly <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 3.3.2 Electrical Properties 3.3.2.1 Electrical Parameters of PRx Coil System Model <\/td>\n<\/tr>\n | ||||||
47<\/td>\n | 3.4 Properties of Mated Coil System Models 3.4.1 Electrical measurement under mated conditions <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | 3.5 Coil Specifications 3.5.1 PRx Coil Specifications <\/td>\n<\/tr>\n | ||||||
54<\/td>\n | 3.5.2 PTx Coil Specifications <\/td>\n<\/tr>\n | ||||||
61<\/td>\n | 4 Power Delivery 4.1 Power Profiles (BPP + MPP) 4.1.1 Specifications 4.1.2 Recommendations 4.1.3 Specification Notes <\/td>\n<\/tr>\n | ||||||
62<\/td>\n | 4.2 Power Receiver Functional Block Diagram 4.2.1 System Model 4.2.1.1 System model PRx circuit topology <\/td>\n<\/tr>\n | ||||||
63<\/td>\n | 4.2.1.2 System model PRx resonance tuning in BPP mode <\/td>\n<\/tr>\n | ||||||
64<\/td>\n | 4.2.1.3 System model resonance tuning in MPP mode 4.2.1.3.1 Rule of thumb <\/td>\n<\/tr>\n | ||||||
65<\/td>\n | 4.2.1.3.2 Selection of resonant capacitors 4.2.1.3.3 FHA analysis: selecting initial values of Ctx <\/td>\n<\/tr>\n | ||||||
68<\/td>\n | 4.2.1.3.4 Time-domain sweep 4.2.1.3.5 Other design considerations 4.2.1.4 PRx electrical properties 4.2.1.5 System model PRx Vrect setting <\/td>\n<\/tr>\n | ||||||
69<\/td>\n | 4.3 Power Transmitter Functional Block Diagram 4.3.1 System Model <\/td>\n<\/tr>\n | ||||||
70<\/td>\n | 4.3.1.1 Definition of inverter phase \u03b8 4.3.1.2 PTx resonant capacitor selection <\/td>\n<\/tr>\n | ||||||
71<\/td>\n | 4.3.1.3 PTx electrical properties <\/td>\n<\/tr>\n | ||||||
72<\/td>\n | 4.4 Operating Frequency 4.4.1 System Model 4.4.2 Specifications 4.5 Object Detection 4.5.1 System Model <\/td>\n<\/tr>\n | ||||||
73<\/td>\n | 4.5.2 Specifications 4.6 Digital Pings 128kHz\/360kHz 4.6.1 Need For Digital Pings 128kHz \/ 360kHz <\/td>\n<\/tr>\n | ||||||
80<\/td>\n | 4.6.2 Specifications 4.6.2.1 PTx Digital Ping Specifications 4.6.2.2 PTx Digital Ping Specifications – 128kHz Ping HB_Low <\/td>\n<\/tr>\n | ||||||
81<\/td>\n | 4.6.2.3 PTx Digital Ping Specifications – 128kHz Ping HB_High 4.6.2.4 PTx Digital Ping Specifications – 128kHz Ping FB 4.6.2.5 PTx Digital Ping Specifications – 360kHz Ping FB <\/td>\n<\/tr>\n | ||||||
82<\/td>\n | 4.6.2.6 PRx Digital Ping Specifications 4.6.2.7 PRx Digital Ping Specifications 4.7 K Estimation 4.7.1 System Model 4.7.1.1 Need For K Estimation <\/td>\n<\/tr>\n | ||||||
83<\/td>\n | 4.7.1.2 Kest Calculation Formula 4.7.1.2.1 E0 and E1 Fit Example <\/td>\n<\/tr>\n | ||||||
84<\/td>\n | 4.7.1.3 Eco-system Scaling <\/td>\n<\/tr>\n | ||||||
85<\/td>\n | 4.7.1.3.1 Subscript nomenclature 4.7.1.3.2 Calculation of Kest Scaling Factors 4.7.1.4 Error stack-up <\/td>\n<\/tr>\n | ||||||
86<\/td>\n | 4.7.2 Specifications <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | 4.8 Output Impedance and Load Transients 4.8.1 System Model 4.8.1.1 Slope of the output Impedance <\/td>\n<\/tr>\n | ||||||
88<\/td>\n | 4.8.1.2 Worst-case tests to measure the slope of the output impedance 4.8.1.2.1 Load step procedure <\/td>\n<\/tr>\n | ||||||
89<\/td>\n | 4.8.1.2.2 Load dump procedure <\/td>\n<\/tr>\n | ||||||
90<\/td>\n | 4.9 Set Pr_max 4.9.1 Background 4.9.2 System Model 4.9.2.1 Theory of Operation 4.9.2.2 PRx ballast current <\/td>\n<\/tr>\n | ||||||
91<\/td>\n | 4.9.2.3 Set Pr_max Flow <\/td>\n<\/tr>\n | ||||||
92<\/td>\n | 4.9.2.3.1 Overall Flow <\/td>\n<\/tr>\n | ||||||
93<\/td>\n | 4.9.2.3.2 Gain Measurement <\/td>\n<\/tr>\n | ||||||
94<\/td>\n | 4.9.2.3.3 Setting initial Vrect_target and Pr_max based on G1*G2 <\/td>\n<\/tr>\n | ||||||
95<\/td>\n | 4.9.2.3.4 Low-k Mode <\/td>\n<\/tr>\n | ||||||
96<\/td>\n | 4.9.3 PTx Specifications 4.9.4 PTx Specification Notes 4.10 Power Transfer Control 4.10.1 Intro and Background (Informative) 4.10.2 System Model 4.10.2.1 Background and Assumptions <\/td>\n<\/tr>\n | ||||||
97<\/td>\n | 4.10.2.1.1 System-level block diagrams 4.10.2.1.2 Design considerations <\/td>\n<\/tr>\n | ||||||
98<\/td>\n | 4.10.2.2 Vrect_target Loop (PRx+PTx) 4.10.2.2.1 PTx Control <\/td>\n<\/tr>\n | ||||||
100<\/td>\n | 4.10.2.3 Ilim Loop (PRx) 4.10.2.3.1 Load Current Control 4.10.2.3.2 Ilim Freeze and Anti-Crash Mechanism <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | 4.10.2.3.3 Loop Update Interval <\/td>\n<\/tr>\n | ||||||
102<\/td>\n | 4.10.2.4 Power throttling 4.10.3 End-to-End Control Specifications 4.10.3.1 Background 4.10.3.2 PTx Specifications <\/td>\n<\/tr>\n | ||||||
103<\/td>\n | 4.10.3.3 PTx Specification Notes <\/td>\n<\/tr>\n | ||||||
104<\/td>\n | 4.10.3.4 PRx Specifications 4.10.3.5 PRx Recommendations <\/td>\n<\/tr>\n | ||||||
105<\/td>\n | 4.10.3.6 PRx Specification Notes 4.11 Mitigation of Side Effects of Cd at MPP Frequency 4.11.1 System Model 4.11.1.1.1 Non-monotonic Vrect\/phase response and output impedance at light load <\/td>\n<\/tr>\n | ||||||
106<\/td>\n | 4.11.1.1.2 Over-voltage mitigation <\/td>\n<\/tr>\n | ||||||
107<\/td>\n | 4.11.1.1.3 Hard switching mitigation <\/td>\n<\/tr>\n | ||||||
108<\/td>\n | 4.11.1.2 Receiver overvoltage protection 4.11.2 Specifications 4.12 Cloak 4.13 Common-mode Noise <\/td>\n<\/tr>\n | ||||||
109<\/td>\n | 5 Communications Physical Layer 5.1 Introduction 5.2 Frequency Shift Keying (PTx to PRx) <\/td>\n<\/tr>\n | ||||||
110<\/td>\n | 5.2.1 System Model 5.2.1.1 FSK Modulator (PTx) 5.2.1.2 FSK Receiver (PRx) <\/td>\n<\/tr>\n | ||||||
112<\/td>\n | 5.2.2 Frequency Shift Keying Specifications <\/td>\n<\/tr>\n | ||||||
113<\/td>\n | 5.3 Amplitude Shift Keying (PRx to PTx) 5.3.1 Modulation Scheme <\/td>\n<\/tr>\n | ||||||
114<\/td>\n | 5.3.2 System Model 5.3.2.1 ASK Modulator (PRx) <\/td>\n<\/tr>\n | ||||||
116<\/td>\n | 5.3.2.2 ASK Receiver (PTx) <\/td>\n<\/tr>\n | ||||||
117<\/td>\n | 5.3.2.3 ASK Modulation Trends <\/td>\n<\/tr>\n | ||||||
119<\/td>\n | 5.3.3 ASK Specifications <\/td>\n<\/tr>\n | ||||||
121<\/td>\n | 6 Foreign Object Detection 6.1 Background 6.2 Open-air Q-Test (pre-power transfer FOD method) 6.2.1 Introduction <\/td>\n<\/tr>\n | ||||||
124<\/td>\n | 6.2.2 Movement Timer 6.2.3 Settling Timer 6.2.4 Glossary 6.2.5 Open-air Q-Test Specifications <\/td>\n<\/tr>\n | ||||||
125<\/td>\n | 6.2.6 Theory of Operation 6.2.6.1 Measuring Q <\/td>\n<\/tr>\n | ||||||
126<\/td>\n | 6.2.6.1.1 Note on PTx with multiple resonant capacitors 6.2.6.1.2 Impact of FO or PRx on Q-deflection 6.2.6.2 Q compensation for drift 6.2.6.2.1 Accentuating Q deflection due to frequency drift caused by FO <\/td>\n<\/tr>\n | ||||||
127<\/td>\n | 6.2.6.2.2 Temperature Compensation 6.2.6.2.3 Separating DC and AC resistance 6.2.6.3 Choosing a Q deflection threshold 6.2.6.4 Potential Implementation Issues 6.2.6.4.1 Proximity to metal objects 6.2.6.4.2 PRx misplaced then replaced <\/td>\n<\/tr>\n | ||||||
128<\/td>\n | 6.2.6.5 Summary <\/td>\n<\/tr>\n | ||||||
129<\/td>\n | 6.2.7 PRx movement and digital ping <\/td>\n<\/tr>\n | ||||||
130<\/td>\n | 6.3 MPP Power Loss Accounting (in-power transfer FOD method) 6.3.1 Introduction <\/td>\n<\/tr>\n | ||||||
131<\/td>\n | 6.3.2 MPLA Specifications 6.3.2.1 MPLA PRx Specifications <\/td>\n<\/tr>\n | ||||||
132<\/td>\n | 6.3.2.2 MPLA PTx Specifications <\/td>\n<\/tr>\n | ||||||
134<\/td>\n | 6.3.2.3 Parameter Representations 6.3.3 MPLA Equations <\/td>\n<\/tr>\n | ||||||
135<\/td>\n | 6.3.4 Eco-System Scaling 6.3.4.1 Introduction <\/td>\n<\/tr>\n | ||||||
136<\/td>\n | 6.3.4.2 Eco-System Scaling Derivation <\/td>\n<\/tr>\n | ||||||
137<\/td>\n | 6.3.5 Process of Extracting LQK-Dependent Coefficients <\/td>\n<\/tr>\n | ||||||
138<\/td>\n | 6.3.5.1 FO power estimation error due to inverter hard switching 6.3.6 FO power estimation error outside 2×2 cylinder <\/td>\n<\/tr>\n | ||||||
139<\/td>\n | 6.3.7 FO Detection Thresholds 6.3.7.1 FO Detection Thresholds <\/td>\n<\/tr>\n | ||||||
140<\/td>\n | 6.3.7.2 pFO Distributions for Scenarios 1 and 2 <\/td>\n<\/tr>\n | ||||||
142<\/td>\n | 6.3.8 In-Power FOD Action 6.3.8.1 FOD Action <\/td>\n<\/tr>\n | ||||||
144<\/td>\n | 6.3.8.2 Power Throttling 6.3.8.3 FOD Action PTx Specifications 6.3.9 Accessory Power Loss Requirements 6.3.9.1 Accessory Power Loss 6.3.10 Error Budget 6.3.10.1 Introduction <\/td>\n<\/tr>\n | ||||||
145<\/td>\n | 6.3.10.2 Measurement Error Analysis <\/td>\n<\/tr>\n | ||||||
147<\/td>\n | 6.3.10.3 pFO Error Budget <\/td>\n<\/tr>\n | ||||||
149<\/td>\n | 6.3.10.4 Is 3-sigma Sufficient? <\/td>\n<\/tr>\n | ||||||
150<\/td>\n | 6.3.10.5 Power Loss Accounting Compliance Testing <\/td>\n<\/tr>\n | ||||||
151<\/td>\n | 6.3.11 Measuring coil current <\/td>\n<\/tr>\n | ||||||
153<\/td>\n | 7 Annex 7.1 PTx Working with Legacy PRx 7.1.1 Background 7.2 Mitigation of Saturation for BPP 7.2.1 System Model 7.2.1.1 Introduction <\/td>\n<\/tr>\n | ||||||
154<\/td>\n | 7.2.1.2 SHO Detection <\/td>\n<\/tr>\n | ||||||
156<\/td>\n | 7.2.1.3 SHO Mitigation 7.2.1.4 Interaction with RPP <\/td>\n<\/tr>\n | ||||||
157<\/td>\n | 7.2.2 SHO Specifications 7.3 Loss-Split Modeling: A framework for calculating localized eddy-current losses 7.3.1 Introduction <\/td>\n<\/tr>\n | ||||||
159<\/td>\n | 7.3.2 Comparison between the standard T-Model and Loss-Split Model <\/td>\n<\/tr>\n | ||||||
160<\/td>\n | 7.3.3 Determining the Loss-Split Model Parameters <\/td>\n<\/tr>\n | ||||||
161<\/td>\n | 7.3.4 Calculating Power Loss using Loss-Split Model <\/td>\n<\/tr>\n | ||||||
162<\/td>\n | 7.3.5 Loss-Split Model Validation 7.4 Resistive Coupling Factor 7.4.1 Introduction 7.4.2 Definition of Mutual Resistance and Kr <\/td>\n<\/tr>\n | ||||||
163<\/td>\n | 7.4.2.1 Loss associated with mutual resistance 7.4.3 Cause of Mutual Resistance <\/td>\n<\/tr>\n | ||||||
164<\/td>\n | 7.4.3.1 Eddy Current Cause 7.4.3.1.1 Physical Meaning of a Negative Mutual Resistance 7.4.3.2 Hysteresis Cause <\/td>\n<\/tr>\n | ||||||
165<\/td>\n | 7.4.4 Why is Kr non-negligible <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" BS EN IEC 63563-10 Qi Specification version 2.0 – Part 10. MPP System Specification (Fast track)<\/b><\/p>\n |