{"id":81246,"date":"2024-10-17T18:52:47","date_gmt":"2024-10-17T18:52:47","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1076-6-2004\/"},"modified":"2024-10-24T19:46:08","modified_gmt":"2024-10-24T19:46:08","slug":"ieee-1076-6-2004","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1076-6-2004\/","title":{"rendered":"IEEE 1076.6 2004"},"content":{"rendered":"

Revision Standard – Inactive – Withdrawn. This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 1076.6-2004 Cover Page <\/td>\n<\/tr>\n
2<\/td>\nTitle Page <\/td>\n<\/tr>\n
4<\/td>\nIntroduction <\/td>\n<\/tr>\n
5<\/td>\nDevelopment of IEEE Std 1076.6-1999 <\/td>\n<\/tr>\n
6<\/td>\nNotice to users
Participants <\/td>\n<\/tr>\n
7<\/td>\nCONTENTS <\/td>\n<\/tr>\n
8<\/td>\n1. Overview
1.1 Scope
1.2 Compliance to this standard <\/td>\n<\/tr>\n
9<\/td>\n1.3 Terminology
1.4 Conventions <\/td>\n<\/tr>\n
10<\/td>\n2. References
3. Definitions and acronyms
3.1 Definitions <\/td>\n<\/tr>\n
11<\/td>\n3.2 Acronyms <\/td>\n<\/tr>\n
12<\/td>\n4. Predefined types
5. Verification methodology <\/td>\n<\/tr>\n
13<\/td>\n5.1 Combinational verification
5.2 Sequential verification <\/td>\n<\/tr>\n
14<\/td>\n6. Modeling hardware elements
6.1 Edge-sensitive sequential logic <\/td>\n<\/tr>\n
26<\/td>\n6.2 Level-sensitive sequential logic <\/td>\n<\/tr>\n
30<\/td>\n6.3 Three-state logic and busses
6.4 Combinational logic <\/td>\n<\/tr>\n
31<\/td>\n6.5 ROM and RAM memories <\/td>\n<\/tr>\n
36<\/td>\n7. Pragmas
7.1 Attributes <\/td>\n<\/tr>\n
53<\/td>\n7.2 Metacomments <\/td>\n<\/tr>\n
54<\/td>\n8. Syntax
8.1 Design entities and configurations <\/td>\n<\/tr>\n
59<\/td>\n8.2 Subprograms and packages <\/td>\n<\/tr>\n
63<\/td>\n8.3 Types <\/td>\n<\/tr>\n
68<\/td>\n8.4 Declarations <\/td>\n<\/tr>\n
74<\/td>\n8.5 Specifications <\/td>\n<\/tr>\n
76<\/td>\n8.6 Names <\/td>\n<\/tr>\n
78<\/td>\n8.7 Expressions <\/td>\n<\/tr>\n
82<\/td>\n8.8 Sequential statements <\/td>\n<\/tr>\n
88<\/td>\n8.9 Concurrent statements <\/td>\n<\/tr>\n
93<\/td>\n8.10 Scope and visibility <\/td>\n<\/tr>\n
94<\/td>\n8.11 Design units and their analysis <\/td>\n<\/tr>\n
95<\/td>\n8.12 Elaboration
8.13 Lexical elements
8.14 Predefined language environment <\/td>\n<\/tr>\n
98<\/td>\nAnnex A
Annex A (informative) Syntax summary <\/td>\n<\/tr>\n
117<\/td>\nAnnex B
Annex B (normative) Synthesis package RTL_ATTRIBUTES <\/td>\n<\/tr>\n
118<\/td>\nIndex
A-M <\/td>\n<\/tr>\n
119<\/td>\nI
K
L
M
O
P
R
S
0-Z <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2004<\/td>\n119<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":81247,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-81246","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/81246","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/81247"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=81246"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=81246"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=81246"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}