{"id":194472,"date":"2024-10-19T12:20:26","date_gmt":"2024-10-19T12:20:26","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1804-2017\/"},"modified":"2024-10-25T04:51:26","modified_gmt":"2024-10-25T04:51:26","slug":"ieee-1804-2017","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1804-2017\/","title":{"rendered":"IEEE 1804 2017"},"content":{"rendered":"
New IEEE Standard – Active. The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting, (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (which comply with this standard) to report fault coverage in a uniform way. This will facilitate the generation of a uniform coverage (and hence a uniform test quality) metric for large chips (including systems-on-chips \u2013 SOCs) with different cores and modules, for which test patterns have been independently generated.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | IEEE Std 1804\u2122-2017 Front cover <\/td>\n<\/tr>\n | ||||||
2<\/td>\n | Title page <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | Important Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | Participants <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | Contents <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 1.\u2002Overview 1.1\u2002Scope 1.2\u2002Purpose <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 1.3\u2002Organization of this document 2.\u2002Definitions, acronyms, and abbreviations 2.1\u2002Definitions <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 2.2\u2002Acronyms and abbreviations 3.\u2002Fault classification and test coverage reporting 3.1\u2002Taxonomy <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 3.2\u2002Classification mnemonics 3.3\u2002Metrics <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 3.4\u2002Illustrations of standard fault classification <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 4.\u2002Fault modeling 4.1\u2002Standard Verilog primitives 4.2\u2002User-defined primitives (UDPs) <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 4.3\u2002Memory models <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 4.4\u2002Flip-flops and latches <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 4.5\u2002Abstract models (including black-box models) 4.6\u2002Fault accounting for IP blocks containing analog components <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | 5.\u2002Fault accounting methods and rules 5.1\u2002Fault accounting rules 5.2\u2002Application of fault accounting standard\u2014common cases <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 6.\u2002Summary <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | Annex\u00a0A (informative) Bibliography <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | Back cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Standard for Fault Accounting and Coverage Reporting(FACR) for Digital Modules<\/b><\/p>\n |