{"id":233749,"date":"2024-10-19T15:14:33","date_gmt":"2024-10-19T15:14:33","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-62433-22017\/"},"modified":"2024-10-25T09:45:13","modified_gmt":"2024-10-25T09:45:13","slug":"bs-en-62433-22017","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-62433-22017\/","title":{"rendered":"BS EN 62433-2:2017"},"content":{"rendered":"

IEC 62433-2:2017 specifies macro-models for an Integrated Circuit (IC) to simulate conducted electromagnetic emissions on a printed circuit board. The model is commonly called Integrated Circuit Emission Model – Conducted Emission (ICEM-CE). The ICEM-CE macro-model can also be used for modelling an IC-die, a functional block and an Intellectual Property (IP) block. The ICEM-CE macro-model can be used to model both digital and analogue ICs. This edition includes the following significant technical changes with respect to the previous edition: Incorporation of an XML based exchange format for model representation.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
2<\/td>\nNational foreword <\/td>\n<\/tr>\n
5<\/td>\nAnnex ZA(normative)Normative references to international publicationswith their corresponding European publications <\/td>\n<\/tr>\n
7<\/td>\nEnglish
CONTENTS <\/td>\n<\/tr>\n
12<\/td>\nFOREWORD <\/td>\n<\/tr>\n
14<\/td>\n1 Scope
2 Normative references
3 Terms, definitions, abbreviations and conventions
3.1 Terms and definitions <\/td>\n<\/tr>\n
16<\/td>\n3.2 Abbreviations
3.3 Conventions
4 Philosophy
4.1 General <\/td>\n<\/tr>\n
17<\/td>\n4.2 Conducted emission from core activity (digital culprit)
4.3 Conducted emission from I\/O activity
4.4 Data exchange format
Figures
Figure 1 \u2013 Decomposition example of a digital IC for conducted emissions analysis <\/td>\n<\/tr>\n
18<\/td>\n5 ICEM-CE basic components
5.1 General
5.2 Internal Activity (IA)
5.2.1 General
Figure 2 \u2013 IA component in the case of a current source <\/td>\n<\/tr>\n
19<\/td>\n5.2.2 Examples of IA
5.3 Passive Distribution Network (PDN)
5.3.1 General
Figure 3 \u2013 Example of IA characteristics in the time domain
Figure 4 \u2013 Example of IA characteristics in the frequency domain <\/td>\n<\/tr>\n
20<\/td>\n5.3.2 Examples of PDN
Figure 5 \u2013 Example of a four-terminal PDN using lumped elements <\/td>\n<\/tr>\n
21<\/td>\n6 IC macro-models
6.1 Types of IC macro-models
6.2 General IC macro-model
Figure 6 \u2013 Example of a seven-terminal PDN using distributed elements
Figure 7 \u2013 Example of a twelve-terminal PDN using matrix representation <\/td>\n<\/tr>\n
22<\/td>\n6.3 Block-based IC macro-model
6.3.1 Block component
Figure 8 \u2013 General IC macro-model <\/td>\n<\/tr>\n
23<\/td>\n6.3.2 Inter-Block Coupling component (IBC)
Figure 9 \u2013 Example of block component with a single IA
Figure 10 \u2013 Example of block components for I\/Os <\/td>\n<\/tr>\n
24<\/td>\n6.3.3 Block-based IC macro-model structure
Figure 11 \u2013 Example of IBC with four internal terminals
Figure 12 \u2013 Relationship between blocks and IBC <\/td>\n<\/tr>\n
25<\/td>\nFigure 13 \u2013 Block-based IC macro-model <\/td>\n<\/tr>\n
26<\/td>\n6.4 Sub-model-based IC macro-model
6.4.1 Sub-model component
Figure 14 \u2013 Example of block-based IC macro-model
Figure 15 \u2013 Example of simple sub-model <\/td>\n<\/tr>\n
27<\/td>\n6.4.2 Sub-model-based IC macro-model structure
Figure 16 \u2013 Sub-model-based IC macro-model <\/td>\n<\/tr>\n
28<\/td>\n7 CEML format
7.1 General
Figure 17 \u2013 CEML inheritance hierarchy <\/td>\n<\/tr>\n
29<\/td>\n7.2 CEML structure
7.3 Global keywords
7.4 Header section <\/td>\n<\/tr>\n
30<\/td>\n7.5 Lead definitions
Tables
Table 1 \u2013 Attributes of Lead keyword in the Lead_definitions section <\/td>\n<\/tr>\n
31<\/td>\n7.6 SPICE macro-models
Table 2 \u2013 Compatibility between the Mode and Type fields for correct CEML annotation
Table 3 \u2013 Subckt definition <\/td>\n<\/tr>\n
33<\/td>\n7.7 Validity section
7.7.1 General
Figure 18 \u2013 Example of a netlist file defining a sub-circuit
Table 4 \u2013 Definition of the Validity section <\/td>\n<\/tr>\n
34<\/td>\n7.7.2 Attribute definitions <\/td>\n<\/tr>\n
36<\/td>\n7.8 PDN
7.8.1 General <\/td>\n<\/tr>\n
37<\/td>\n7.8.2 Attribute definitions
Table 5 \u2013 Definition of the Lead keyword for Pdn section <\/td>\n<\/tr>\n
40<\/td>\nTable 6 \u2013 Valid data formats and their default units in the Pdn section
Table 7 \u2013 Valid file extensions in the Pdn section <\/td>\n<\/tr>\n
41<\/td>\n7.8.3 Description
Table 8 \u2013 Valid fields of the Lead keyword in the Pdn section <\/td>\n<\/tr>\n
43<\/td>\nFigure 19 \u2013 PDN represented as S-parameters in Touchstone format <\/td>\n<\/tr>\n
44<\/td>\nTable 9 \u2013 Netlist definition <\/td>\n<\/tr>\n
45<\/td>\n7.9 IBC
7.9.1 General
7.9.2 Attribute definitions <\/td>\n<\/tr>\n
46<\/td>\nTable 10 \u2013 Differences between the Pdn and Ibc section fields
Table 11 \u2013 Valid fields of the Lead keyword for IBC definition <\/td>\n<\/tr>\n
47<\/td>\n7.10 IA
7.10.1 General
7.10.2 Attribute definitions
Table 12 \u2013 Definition of the Lead keyword in the Ia section <\/td>\n<\/tr>\n
48<\/td>\nTable 13 \u2013 Voltage and Current definition
Table 14 \u2013 Valid file extensions in the Ia section <\/td>\n<\/tr>\n
49<\/td>\nTable 15 \u2013 Definition of the Pulse keyword in the Voltage or Current section
Table 16 \u2013 Base units of the Pulse section\u2019s fields <\/td>\n<\/tr>\n
50<\/td>\nFigure 20 \u2013 Simulated IA waveform with corresponding parameters <\/td>\n<\/tr>\n
51<\/td>\n7.10.3 Description
Table 17 \u2013 Valid data formats and their default units for the Voltage and Current elements <\/td>\n<\/tr>\n
52<\/td>\n8 Requirements for parameter extraction
8.1 General
8.2 Environmental extraction constraints
8.3 IA parameter extraction
8.4 PDN parameter extraction <\/td>\n<\/tr>\n
53<\/td>\n8.5 IBC parameter extraction <\/td>\n<\/tr>\n
54<\/td>\nAnnex\u00a0A (normative)Preliminary definitions for XML representation
A.1 XML basics
A.1.1 XML declaration
A.1.2 Basic elements
A.1.3 Root element <\/td>\n<\/tr>\n
55<\/td>\nA.1.4 Comments
A.1.5 Line terminations
A.1.6 Element hierarchy
A.1.7 Element attributes
A.2 Keyword requirements
A.2.1 General <\/td>\n<\/tr>\n
56<\/td>\nA.2.2 Keyword characters
A.2.3 Keyword syntax
A.2.4 File structure <\/td>\n<\/tr>\n
57<\/td>\nFigure A.1 \u2013 Multiple XML (CEML) files
Figure A.2 \u2013 XML files with data files (*.dat) <\/td>\n<\/tr>\n
58<\/td>\nA.2.5 Values
Figure A.3 \u2013 XML files with additional files <\/td>\n<\/tr>\n
59<\/td>\nTable A.1 \u2013 Valid logarithmic units <\/td>\n<\/tr>\n
61<\/td>\nAnnex\u00a0B (normative)CEML valid keywords and usage
B.1 Root element keywords <\/td>\n<\/tr>\n
62<\/td>\nB.2 File header keywords <\/td>\n<\/tr>\n
63<\/td>\nB.3 Validity section keywords <\/td>\n<\/tr>\n
64<\/td>\nB.4 Global keywords
B.5 Lead Keyword <\/td>\n<\/tr>\n
65<\/td>\nB.6 Lead_definitions section attributes
B.7 Macromodels section attributes <\/td>\n<\/tr>\n
66<\/td>\nB.8 Pdn section keywords
B.8.1 Lead element keywords <\/td>\n<\/tr>\n
68<\/td>\nB.8.2 Netlist section keywords
B.9 Ibc section keywords
B.9.1 Lead element keywords <\/td>\n<\/tr>\n
70<\/td>\nB.9.2 Netlist section keywords
B.10 Ia section keywords
B.10.1 Lead element keywords <\/td>\n<\/tr>\n
71<\/td>\nB.10.2 Voltage section keywords <\/td>\n<\/tr>\n
73<\/td>\nB.10.3 Current section keywords <\/td>\n<\/tr>\n
75<\/td>\nAnnex\u00a0C (informative)Example of ICEM-CE macro-model in CEML format
C.1 General
C.2 PDN and IBC sub-model
Figure C.1 \u2013 Example pin-out of a microcontroller and the modelled pins <\/td>\n<\/tr>\n
76<\/td>\nC.3 IA sub-model
Figure C.2 \u2013 PDN sub-model topology <\/td>\n<\/tr>\n
77<\/td>\nFigure C.3 \u2013 IA sub-model topology
Figure C.4 \u2013 IA of digital block in frequency domain <\/td>\n<\/tr>\n
78<\/td>\nC.4 Frequency domain ICEM-CE in CEML
Figure C.5 \u2013 IA of digital block in time domain <\/td>\n<\/tr>\n
80<\/td>\nC.5 Time domain ICEM-CE in CEML <\/td>\n<\/tr>\n
82<\/td>\nAnnex\u00a0D (informative)Conversions between parameter types
D.1 General
D.2 Conversion for one-port PDN
D.3 Conversion for two-port PDN
Table D.1 \u2013 One-port conversion <\/td>\n<\/tr>\n
83<\/td>\nTable D.2 \u2013 Two-port conversion <\/td>\n<\/tr>\n
84<\/td>\nAnnex\u00a0E (informative)Model parameter generation
E.1 General
E.2 Default structure and values
E.2.1 General
E.2.2 IA parameters <\/td>\n<\/tr>\n
85<\/td>\nE.2.3 PDN parameters
Table E.1 \u2013 Typical parameters for CMOS logic technologies
Table E.2 \u2013 Typical number of logic gates vs. CPU technology <\/td>\n<\/tr>\n
86<\/td>\nE.3 Model parameter generation from design information
E.3.1 General
E.3.2 IA parameters
Table E.3 \u2013 R, L and C parameters for various package types <\/td>\n<\/tr>\n
87<\/td>\nFigure E.1 \u2013 Typical characterization current gate schematic
Figure E.2 \u2013 Current peak during switching transition <\/td>\n<\/tr>\n
88<\/td>\nFigure E.3 \u2013 Example of IA extraction procedure from design
Figure E.4 \u2013 Technology Influence <\/td>\n<\/tr>\n
89<\/td>\nFigure E.5 \u2013 Final current waveform for a program period
Figure E.6 \u2013 Comparison between measurement and simulation <\/td>\n<\/tr>\n
90<\/td>\nE.3.3 PDN parameters
Figure E.7 \u2013 Example lumped element model of a package <\/td>\n<\/tr>\n
92<\/td>\nE.4 Model parameter generation from measurements
E.4.1 IA parameters
Figure E.8 \u2013 Circuit structure of the netlist <\/td>\n<\/tr>\n
93<\/td>\nFigure E.9 \u2013 Principle of the IA computation in the frequency domain <\/td>\n<\/tr>\n
94<\/td>\nFigure E.10 \u2013 Process involved to model iA(t)
Figure E.11 \u2013 iExt(t) measured using IEC\u00a061967-4 <\/td>\n<\/tr>\n
95<\/td>\nE.4.2 PDN parameters
Figure E.12 \u2013 iA(t)and iExt(t) profiles
Figure E.13 \u2013 Conventional one-port S-parameter measurement <\/td>\n<\/tr>\n
96<\/td>\nFigure E.14 \u2013 Two-port method for low impedance measurement
Figure E.15 \u2013 Two-port method for high impedance measurement <\/td>\n<\/tr>\n
97<\/td>\nFigure E.16 \u2013 Example of a hardware set-up used to extract the PDN parameters <\/td>\n<\/tr>\n
98<\/td>\nFigure E.17 \u2013 Miniature 50 \u2126 coaxial connectors
Figure E.18 \u2013 Impedance probe using two miniature coaxial connectors
Figure E.19 \u2013 Open and short terminations <\/td>\n<\/tr>\n
99<\/td>\nFigure E.20 \u2013 Measurement probe model
Figure E.21 \u2013 De-embedding principle <\/td>\n<\/tr>\n
100<\/td>\nFigure E.22 \u2013 Example of a predefined PDN structure
Table E.4 \u2013 Measurement configurations and extracted RLC parameters <\/td>\n<\/tr>\n
101<\/td>\nFigure E.23 \u2013 RL configuration <\/td>\n<\/tr>\n
102<\/td>\nFigure E.24 \u2013 RLC configuration
Figure E.25 \u2013 RLC with magnetic coupling configuration
Figure E.26 \u2013 Impedance seen from Vcc and Gnd <\/td>\n<\/tr>\n
103<\/td>\nFigure E.27 \u2013 Complete PDN component <\/td>\n<\/tr>\n
104<\/td>\nFigure E.28 \u2013 Set-up for correlation (left), measurement and prediction model (right)
Figure E.29 \u2013 Set-up used to measure the internal decoupling capacitor <\/td>\n<\/tr>\n
105<\/td>\nAnnex\u00a0F (informative)Decoupling capacitors optimization
Figure F.1 \u2013 Equivalent schematic of the complete electronic system <\/td>\n<\/tr>\n
106<\/td>\nFigure F.2 \u2013 Impedance prediction and measurements <\/td>\n<\/tr>\n
107<\/td>\nAnnex\u00a0G (informative)Conducted emission prediction
Figure G.1 \u2013 IEC\u00a061967-4 test set-up standard
Figure G.2 \u2013 Comparison between prediction and measurement <\/td>\n<\/tr>\n
108<\/td>\nAnnex\u00a0H (informative)Conducted emission prediction at PCB level
Figure H.1 \u2013 Prediction of ETVddc noise level at PCB level <\/td>\n<\/tr>\n
109<\/td>\nFigure H.2 \u2013 Good agreements on the noise envelope <\/td>\n<\/tr>\n
110<\/td>\nBibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

EMC IC modelling – Models of integrated circuits for EMI behavioural simulation. Conducted emissions modelling (ICEM-CE)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2017<\/td>\n112<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":233750,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2641],"product_tag":[],"class_list":{"0":"post-233749","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-bsi","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/233749","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/233750"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=233749"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=233749"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=233749"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}