| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 5<\/td>\n | Annex ZA (normative)Normative references to international publicationswith their corresponding European publications <\/td>\n<\/tr>\n | ||||||
| 7<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | INTRODUCTION Figures Figure 1 \u2013 IEC 62386 graphical overview <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | 1 Scope 2 Normative references <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 4 General 4.1 Purpose 4.2 Version number 4.3 System structure and architecture Tables Table 1 \u2013 System components <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | 4.4 System information flow 4.5 Command types Figure 2 \u2013 System structure example Figure 3 \u2013 Communication between bus units (example) <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | 4.6 Bus units 4.6.1 Transmitters and receivers in bus units 4.6.2 Control gear 4.6.3 Input device Table 2 \u2013 Transmitters and receivers in bus units <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | 4.6.4 Single-master application controller 4.6.5 Multi-master application controller 4.6.6 Sharing an interface <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | 4.6.7 Power for operation Figure 4 \u2013 Example of a shared interface <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | 4.7 Bus power supply and load calculations 4.7.1 Current demand coverage 4.7.2 Maximum signal current compliance 4.7.3 Simplified system calculation 4.8 Wiring 4.8.1 Wiring structure 4.8.2 Wiring specification <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | 4.9 Electrical safety requirements 4.9.1 General 4.9.2 Insulation 4.9.3 Electric strength 4.9.4 Limitation of the touch current from the device to the bus <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | 4.10 Earthing of the bus 4.11 Power interruptions at bus units 4.11.1 Different levels of power interruptions 4.11.2 Short power interruptions of external power supply Table 3 \u2013 Power-interruption timing of external power Table 4 \u2013 Power-interruption timing of bus power <\/td>\n<\/tr>\n | ||||||
| 29<\/td>\n | 4.11.3 External power cycle 4.11.4 Short interruptions of bus power supply 4.11.5 Bus power down 4.11.6 System start-up timing Table 5 \u2013 Short power interruptions <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | Figure 5 \u2013 Start-up timing example Table 6 \u2013 Start-up timing <\/td>\n<\/tr>\n | ||||||
| 31<\/td>\n | 5 Electrical specification 5.1 General 5.2 Marking of the interface 5.3 Capacitors between the interface and earth 5.4 Signal voltage rating Table 7 \u2013 System voltage levels <\/td>\n<\/tr>\n | ||||||
| 32<\/td>\n | 5.5 Signal current rating 5.6 Marking of bus powered bus unit Table 8 \u2013 Receiver voltage levels Table 9 \u2013 Transmitter voltage levels Table 10 \u2013 Current rating <\/td>\n<\/tr>\n | ||||||
| 33<\/td>\n | 5.7 Signal rise time and fall time Figure 6 \u2013 Maximum signal rise and fall time measurements Table 11 \u2013 Signal rise and fall times <\/td>\n<\/tr>\n | ||||||
| 34<\/td>\n | 6 Bus power supply 6.1 General 6.2 Marking of the bus power supply terminals 6.3 Capacitors between the interface and earth 6.4 Voltage rating Figure 7 \u2013 Minimum signal rise and fall time measurements <\/td>\n<\/tr>\n | ||||||
| 35<\/td>\n | 6.5 Current rating 6.5.1 General current rating 6.5.2 Single bus power supply current rating 6.5.3 Integrated bus power supply current rating 6.5.4 Dynamic behaviour of the bus power supply Table 12 \u2013 Bus power supply output voltage Table 13 \u2013 Bus power supply current rating <\/td>\n<\/tr>\n | ||||||
| 36<\/td>\n | Figure 8 \u2013 Bus power supply current behaviour Table 14 \u2013 Bus power supply dynamic behaviour <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | 6.6 Bus power supply timing requirements 6.6.1 Short power supply interruptions 6.6.2 Short circuit behaviour Figure 9 \u2013 Bus power supply voltage behaviour Table 15 \u2013 Short circuit timing behaviour <\/td>\n<\/tr>\n | ||||||
| 38<\/td>\n | 7 Transmission protocol structure 7.1 General 7.2 Bit encoding 7.2.1 Start bit and data bit encoding 7.2.2 Stop condition encoding 7.3 Frame description Figure 10 \u2013 Frame example Figure 11 \u2013 Bi-phase encoded bits <\/td>\n<\/tr>\n | ||||||
| 39<\/td>\n | 7.4 Frame types 7.4.1 16-bit forward frame 7.4.2 24-bit forward frame 7.4.3 32-bit forward frame 7.4.4 Reserved forward frame 7.4.5 Backward frame 7.4.6 Proprietary forward frames <\/td>\n<\/tr>\n | ||||||
| 40<\/td>\n | 8 Timing 8.1 Single-master transmitter timing 8.1.1 Single-master transmitter bit timing 8.1.2 Single-master transmitter frame sequence timing Figure 12 \u2013 Bit timing example Figure 13 \u2013 Settling time illustration Table 16 \u2013 Transmitter bit timing <\/td>\n<\/tr>\n | ||||||
| 41<\/td>\n | 8.2 Receiver timing 8.2.1 Receiver bit timing Table 17 \u2013 Transmitter settling time values <\/td>\n<\/tr>\n | ||||||
| 42<\/td>\n | 8.2.2 Receiver bit timing violation Figure 14 \u2013 Receiver timing decision example Table 18 \u2013 Receiver timing starting at the beginning of a logical bit Table 19 \u2013 Receiver timing starting at an edge inside of a logical bit <\/td>\n<\/tr>\n | ||||||
| 43<\/td>\n | 8.2.3 Receiver frame size violation 8.2.4 Receiver frame sequence timing 8.2.5 Reception of backward frames Table 20 \u2013 Receiver settling time values <\/td>\n<\/tr>\n | ||||||
| 44<\/td>\n | 8.3 Multi-master transmitter timing 8.3.1 Multi-master transmitter bit timing 8.3.2 Multi-master transmitter frame sequence timing Table 21 \u2013 Multi-master transmitter bit timing <\/td>\n<\/tr>\n | ||||||
| 45<\/td>\n | 9 Method of operation 9.1 Dealing with frames and commands 9.1.1 General Table 22 \u2013 Multi-master transmitter settling time values <\/td>\n<\/tr>\n | ||||||
| 46<\/td>\n | 9.1.2 Frame received or rejected 9.1.3 Frame accepted or ignored 9.1.4 Command accepted or ignored 9.1.5 Command executed or discarded Figure 15 \u2013 Dealing with frames and commands <\/td>\n<\/tr>\n | ||||||
| 47<\/td>\n | 9.2 Collision avoidance, collision detection and collision recovery 9.2.1 General 9.2.2 Collision avoidance 9.2.3 Collision detection <\/td>\n<\/tr>\n | ||||||
| 48<\/td>\n | Table 23 \u2013 Checking a logical bit, starting at an edge at the beginning of the bit Table 24 \u2013 Checking a logical bit, starting at an edge inside the bit <\/td>\n<\/tr>\n | ||||||
| 49<\/td>\n | 9.2.4 Collision recovery Figure 16 \u2013 Collision detection timing decision example Table 25 \u2013 Collision recovery timing <\/td>\n<\/tr>\n | ||||||
| 50<\/td>\n | 9.3 Transactions 9.4 Send-twice forward frames and send-twice commands Figure 17 \u2013 Collision recovery example <\/td>\n<\/tr>\n | ||||||
| 51<\/td>\n | 9.5 Command iteration 9.6 Usage of a shared interface 9.6.1 General Table 26 \u2013 Transmitter command iteration timing Table 27 \u2013 Receiver command iteration timing <\/td>\n<\/tr>\n | ||||||
| 52<\/td>\n | 9.6.2 Backward frames 9.6.3 Forward frames 9.7 Use of multiple bus power supplies 10 Declaration of variables 11 Definition of commands <\/td>\n<\/tr>\n | ||||||
| 53<\/td>\n | Annex A (informative) Background information for systems A.1 Wiring information <\/td>\n<\/tr>\n | ||||||
| 54<\/td>\n | A.2 System architectures A.2.1 General A.2.2 Single-master architecture Table A.1 \u2013 Maximum cable length <\/td>\n<\/tr>\n | ||||||
| 55<\/td>\n | A.2.3 Multi-master architecture with one application controller Figure A.1 \u2013 Single-master architecture example <\/td>\n<\/tr>\n | ||||||
| 56<\/td>\n | A.2.4 Multi-master architecture with more than one application controller Figure A.2 \u2013 Multi-master architecture example with one application controller <\/td>\n<\/tr>\n | ||||||
| 57<\/td>\n | A.2.5 Multi-master architecture with integrated input device Figure A.3 \u2013 Multi-master architecture example with two application controllers <\/td>\n<\/tr>\n | ||||||
| 58<\/td>\n | A.2.6 Multi-master architecture with integrated input device and power supply Figure A.4 \u2013 Multi-master architecture example with integrated input device <\/td>\n<\/tr>\n | ||||||
| 59<\/td>\n | A.3 Collision detection Figure A.5 \u2013 Multi-master architecture example with integratedinput device and bus power supply <\/td>\n<\/tr>\n | ||||||
| 60<\/td>\n | A.4 Timing definition explanations A.4.1 General A.4.2 Receiver timing A.4.3 Transmitter timing Figure A.6 \u2013 Collision detection timing diagram <\/td>\n<\/tr>\n | ||||||
| 61<\/td>\n | A.4.4 Grey areas A.5 Maximum current consumption calculation explanation A.5.1 Single bus power supply Figure A.7 \u2013 Transmitter and receiver timing illustration <\/td>\n<\/tr>\n | ||||||
| 62<\/td>\n | A.5.2 Multiple bus power supplies Figure A.8 \u2013 Bus power supply current values Figure A.9 \u2013 Current demand coverage <\/td>\n<\/tr>\n | ||||||
| 63<\/td>\n | A.5.3 Redundant bus power supplies Figure A.10 \u2013 Combination of four bus power supplies Figure A.11 \u2013 Redundant bus power supplies <\/td>\n<\/tr>\n | ||||||
| 64<\/td>\n | A.6 Communication layer overview A.6.1 General Table A.2 \u2013 OSI layer model of the IEC 62386 series <\/td>\n<\/tr>\n | ||||||
| 65<\/td>\n | A.6.2 Physical layer A.6.3 Data link layer A.6.4 Network layer A.6.5 Transport layer A.6.6 Session layer A.6.7 Presentation layer A.6.8 Application layer A.7 Effects of combining version number 1 and version number 2.y devices <\/td>\n<\/tr>\n | ||||||
| 66<\/td>\n | Table A.3 \u2013 Effects of combining version number 1 and version number 2.y devices <\/td>\n<\/tr>\n | ||||||
| 67<\/td>\n | Annex B (informative) Touch current Figure B.1 \u2013 Touch current from a bus unit Figure B.2 \u2013 Summation of touch currents from several bus units <\/td>\n<\/tr>\n | ||||||
| 68<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Digital addressable lighting interface – General requirements. System components<\/b><\/p>\n |